Malik Najmus Siraj siraj@case.edu.pk Digital Logic Design Malik Najmus Siraj siraj@case.edu.pk

Digital Logic Design@CASE by Najmus Siraj Today’s Agenda Recap State machine task Registers JK flip flop and T flip Flop Counter with state machine Counters State machine with JK and T flip flop One hot encoding Digital Logic Design@CASE by Najmus Siraj

Characteristic table and Equation Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Design a circuit that meets the following specifications: The circuit has one input, w, and one output, z. All changes in the circuit occur on the positive edge of the clock signal. Output z=1 if the input was 1 during the two immediately preceding clock cycles. You are required to Design the following things State machine State Table Minimized circuit diagram (Use K-map to minimize equations). State machine task Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

State machine using JK flip flop Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj One hot encoding Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj JK flip flop example Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Counters Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Ripple counter Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Ripple counter Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Synchronous counter Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Up down counter Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Ring counter Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj State Reduction Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Serial data transfer Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Shift register Digital Logic Design@CASE by Najmus Siraj

Serial transfer example Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Serial addition Digital Logic Design@CASE by Najmus Siraj

Maximum Register to Register delay G10 TCQ + G7 Tpd + G6 Tpd + G8 Tpd + G10 Tsu = 3 + 4 + 4 + 4 + 2 = 17ns Maximum clock to out delay G5 Tpd + G10 TCQ + G7 Tpd + G6 Tpd + G8 Tpd + G11 Tpd + G13 Tpd = = 5 + 3 + 4 + 4 + 4+ 4 + 5 = 29 ns Maximum pin to pin delay (that is not clock to out delay) G4 Tpd + G7 Tpd + G6 Tpd + G8 Tpd + G11 Tpd + G13 Tpd = 5 + 4+ 4 + 4 + 4 + 5 = 26 ns Setup time on B input G2 Tpd + G6 Tpd +G8 Tpd + G10 Tsu – G5 Tpd = 5 + 4 + 4 + 2 – 5 = 10ns