Electromagnetic compatibility of ICs Seminar Alexandre Boyer Senior lecturer Sonia Ben Dhia Associate professor & 07/2007 September 18

Summary Introduction & EMC overview EMC Basics concepts Measurement methods EMC Models EMC Guidelines Case study EMC Challenges & Conclusion September 18 Mai 2007

Introduction & EMC overview

Technology Scale Down Channel length Channel length divided by 2 each 18 month in the 90’s Research has 5 year advance on industry September 18

Multicore, DSP, FPGA, RF multiband Technology Scale Down System on chip Technology 0.18µm 0.12µm 90nm 65nm 45nm Complexity 50M 100M 250M 500M 1G Packaging 1999 2001 2003 2005 2007 16bit µC 0.5 A 32bit µC 2 A µC+DSP 10 A µC+DSP+.. Flash,eRam 30 A Multicore, DSP, FPGA, RF multiband 100 A Embedded blocks transient current 2007: Package on package: de + en + Trend: Increase of complexity, IOs number, operating frequencies, transient current September 18

EMC introduction Why EMC of IC ? Since mid 80’s, printed circuit board designers have put continuous efforts in reducing parasitic emission and interference coupling within their systems Until mid 90’s, IC designers had no consideration about EMC problems in their design.. Many EMC problems originate from ICs With the increased clock speed and chip size, IC generate increased amount of noise  EMC must be handled at IC level. September 18

Customer’s specifications EMC introduction EMC of IC research topics Improve or develop EMC measurement methods to respond to new customer’s requests Develop simulation tools to predict EMC of IC behavior Develop design guidelines aiming at reducing emission and susceptibility levels Emission level measurement Simulation Customer’s specifications IC emission spectrum Target frequency September 18

Printed circuit boards EMC Introduction Two main concepts: Susceptibility to EM waves Emission of EM waves Components Printed circuit boards Equipments System Noise Personnal entrainments Safety systems interferences Susceptibility to radio frequency interference is illustrate in the case of a very high radar wave illuminating an airplane. This situation is very common at the proximity of airports. A Giga-watt pulse is received by the the plane, which captures some energy which may flow to the equipment, the board and finally to the component. On the other hand, the parasitic emission due to the integrated circuit inside a car may jeopardize the correct behavior of personal devices such as mobile phones, and RF links. In some case, the parasitic energy may be high enough to parasite the safety systems of the car. Hardware fault Software failure Function Loss September 18

The EM wave propagates through the air EMC Introduction Coupling mechanisms: Conducted mode Radiated mode The VDD supply propagates parasits The EM wave propagates through the air Two main coupling mechanisms may be distinguished: the conducted mode and the radiated mode. In conducted mode, the the parasitic perturbations are propagated from the main sources to the victims by interconnects. The supply lines are the main contributors to such coupling, as they are shared by several integrated circuits. Conducted coupling is the most common problem. In the case of radiated mode, the source is able to generate a strong radiated energy, that couple through the air to a victim integrated circuit. Several cases radiated coupling may be found in electronic systems with embedded radio-frequency sources (Mobile phones for example). Power Integrity (PI) Electromagnetic Interference (EMI) September 18

Origin of Parasitic Emission Basic mechanisms for core current: CMOS inverter exemple VDD Switching current IDD (0.1mA) IDD (0.1mA) ISS (0.1mA) Vin Voltage Time Output capa VOUT VSS ISS (0.1mA) Time One of the major source of perturbation is the current flowing inside each elementary gate of the integrated circuit. Let us consider the CMOS inverter, supplied by a high voltage VDD (2V in 0.18µm) and ground VSS (0V). When the input falls to 0 (i.e logic level “0”), a current (around 0.5mA) charges the capacitance through the pull up device. When the input rises to 2V, that is a logic level “1”, a similar current flows through the pull down device and discharges the capacitance. September 18

Origin of Parasitic Emission The increasing speed and the high level of integration generate a stronger noise: 50ps i(t) Time Vdd Vdd i(t) Vss Vss Internal switching noise Switching gates Simultaneous Switching Noise Main noise sources comes from AC current sources: Clock-driven blocks, synchronized logic Memory read/write/refresh I/O switching September 18

Increase parasitic noise Origin of Parasitic Emission Why technology scale down makes things worse ? Time New process Volt Old process Current level keeps almost constant but: Faster current switching Stronger di/dt Increase parasitic noise Current di/dt Old process Reduc Voltage swing => less E field With the technology scale down, the supply voltage is reduced and the signals switch faster within interconnects (From voltage to scaled voltage). In 0.18µm technology, the switching is about 100ps (Pico-second or 10-12 second), with a 2V swing. Concerning currents, the amplitude of elementary peaks appearing on supply lines of each elementary gates are sharper, but their amplitude remains constant (0.5mA in 100ps, per gate). Consequently, stronger di/dt are observed, leading to increased emission problems. New process Time September 18

Origin of Parasitic Emission Example: evaluation of switching current in an IC 0.1 mA / gate in 100ps 1 Million gates in 32 Bit Micro => 100A 10% switching activity => 10A 10% current peak spread (non synchronous switching) => 1A in 250ps 0.1 mA Ampere 0.1 ns time Vdd Vss i(t) Current / gate Ampere 0.25 ns time Current / Ic 1 A 0.1 ma/gate in 100 ps, 10 million (base band), 10 K(8bits), 100K (16 bits), 1M (32 bits). % switching activity = 10 %, /10 because spread current = 1 A peak sur 1 ns. 16 bits : 100 mA sur 1 ns, 32 bits = 1A 500 ps… September 18

Susceptibility issue Power supply decrease & Noise margin reduction : => Increase of ICs sensibility to parasitic noise Supply (V) 5.0 3.3 2.5 I/O 1.8 1.2 Tension cœur: réduire la puissance consommée, fragilité des oxyde Tension I/O: reduction => aller + vite de 0 à VDD, mais – rapide pour des raison de compatibilité entre techno 0.8 Core 0.5µm 0.35µm 0.18µm 90nm 65nm 45nm Technology September 18

Susceptibility Issues Less noise margin : => 100mV in 2015 !!!! Supply voltage 10V External voltage 90nm 0.25m 1V 45nm 32nm 0.18m 0.13m 22 nm 18 nm 65nm Internal voltage Noise margin 0.1V Year 1995 2000 2005 2010 2015 September 18

Susceptibility Issues 1-10GHz : Packages act as very good antennas EMC of ICs issues La longueur d’onde est de 10cm a 3GHz et l’antenne optimale a une taille de 25mm (lamda/4) Le boitier est une bonne antenne en émission et réception dans ces bandes de fréquence September 18

Susceptibility Issues Multiple parasitic electromagnetic sources Components issues Power HF VHF UHF SHF xHF THF 1GW Radar Météo Radars Satellites 1MW TV UHF MWave 1KW TV VHF Stat. de base Badge Hobby 1W GSM UMTS Multitude de sources de puissance différente entre 30MHz et 30GHz => la bande de fréquence dangereuse est très large et les modes d’agression sont très varies (continu, impulsionnel), la distance à l’émetteur varie aussi du km au cm => problème complexe et de moins en moins déterministe (multiplicité de cas) Radar Hobby DECT 1mW Frequency 3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 300 GHz September 18

EMC environment EMC for Integrated Circuits requires various expertise High frequency measurement High frequency modelling 2D, 3D modelling Electrical modelling IC design IC floorplan Caleidoscope du materiel etrange de la CEM September 18