Intel Vendor Update IDC HPC Users Forum, Houston, Tx April 7, 2011 Stephen R. Wheat, Ph.D. Sr. Director, HPC Worldwide Business Operations Data Center Group (DCG) Intel Corporation

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Silicon Technology Leadership Intel Execution on a 2-Year Cycle 90nm 2003 65nm 2005 2005 – 2012 45nm 2007 32nm 2009 22nm 2011 This foil contains microscopic photos of real nanoscale transistors and shows how Intel will continue to deliver on Moore’s Law for many years to come. Intel leads the industry producing silicon with 90 nm process technology, and is headed toward volume production on 65 nm process technology. Intel’s 65 nm logic technology incorporates industry-leading performance features such as 35 nm gate lengths, strained silicon and low-k dielectric. Roadmap processes include 65 nm – 23 nm nodes. In addition Intel is also investigating silicon technology in the 16 nm - 6 nm node range Important power saving techniques are included, such as low gate capacitance, low interconnect capacitance and sleep transistors for leakage reduction. The 65 nm technology is being demonstrated on 70 Mbit SRAM chips using a 0.57 mm2 cell size and >0.5 billion transistors. Intel is on track for being the first to produce 65 nm generation microprocessor products in 2005 2013 –2017 14nm 2013 11nm 2015 8nm 2017 Research 25 nm 15nm New Intel technology generation every 2 years Intel R&D technologies drive this pace well into the next decade Roadmap All products, computer systems, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice.

High Performance Micro-Architecture for HPC Tick Tock Tick Tock Tick Tock Tick Tock 65nm 45nm 32nm 22nm Core™ Harpertown Penryn Nehalem Westmere Sandy Bridge Future tick Future tock New instructions: SSSE3 SSE4.1 SSE4.2 AES AVX Future - FMA Tick-tock in action Year 1: First the "Tick“ (SHRINK) Intel delivers new silicon process technology, dramatically increasing transistor density while enhancing performance and energy efficiency within a smaller, more refined version of our existing microarchitecture. Year 2: Then the "Tock“ (NEW microarch) Intel delivers entirely new processor microarchitecture to optimize the value of the increased number of transistors and technology updates now available. Intel Advanced Vector Extensions (AVX). Intel® AVX is a new 256 bit instruction set extension to SSE and is designed for applications that are Floating Point (FP) intensive. It will be released in 2010 as part of the Sandy Bridge processor family and will be present in platforms ranging from notebooks to servers. Intel AVX improves performance due to wider vectors, new extensible syntax, and rich functionality. This results in better management of data and general purpose applications like image, audio/video processing, scientific simulations, financial analytics and 3D modeling and analysis. SNB: Integrated PCI on socket so no more need for IOH. Turbo boost is dynamic – measures power load over longer period of time. (Intel® AVX), a 256 bit extension to Streaming SIMD Extensions (SSE) designed for applications that are floating point intensive SNB improvements: Integrated PCI Express* 3.0 Optimized Turbo Boost Intel Advanced Vector Extensions (AVX)

HPC Award Program Goals Title of Presentation Client #1 Help to expand the use of HPC by showing real ROI examples: Expand the “Missing Middle” – SMBs, SMSs, etc. by providing examples of what can be done with HPC Show mainstream and leading edge HPC success stories #2 Create a large database of success stories across many industries/verticals/disciplines To help justify investments and show non-users ideas on how to adopt HPC in their environment Creating many examples for funding bodies and politicians to use and better understand the value of HPC  to help grow public interest in expanding HPC investments For OEMs to demonstrate success stories using their products Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

Overall Approach: Multiple Awards To Address Different HPC Users Title of Presentation Client The awards could be given out every six months and there would be a number of different categories: Small and Start-up Organizations Mainstream Organizations The Award lists would also be split by industry and perhaps by discipline The number of “Top” awards would be limited to keep the awards being valuable But award certificates would be given to all submissions that met the base qualifications Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

Users Have to Submit the Value of the Accomplishment Title of Presentation Client Users would be required to submit the value achieved with their HPC system, using 3 broad categories, following a very specific set of guidelines: a) Dollar value of the HPC usage e.g. made $$$ in new revenues, saved $$$ in costs, made $$$ in profits, etc. b) Scientific or engineering accomplishment e.g. discovered how xyz really works, develop a new drug that does xyz, etc. c) Value to society as a whole e.g. ended nuclear testing, made something safer, provided protection against xyz, etc. … and the investment in HPC that was required (in order to calculate the ROI) Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

The Judgment Process Has To Be Clear, Fair And Transparent Title of Presentation Client The ranking of the accomplishments would be done by only HPC USERS, following very specific rules. A three step process is proposed: First the submission has to be complete with a clear “Value” shown Secondly, a quick assessment could be made to see that it is a realistic assessment of the value/returns -- We suggest that the HPC User Forum steering committee could be a starting point Then the final evaluation would be by experts in the specific area/discipline Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

Award Types for Different Categories Title of Presentation Client For SMBs: Awards would include CPU hours, software and consulting time For Mainstream HPC Sites: A Trophy or Certificate at various events such as HPC User Forum, vertical conferences, SC and ISC Awards certificates would include the logo’s of all organizations involved Winners would be invited to present their success at HPC User Forums, SC and ISC and other venues Partner publications would help run the awards PR Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

List of Potential Press / Media Partners Title of Presentation Client Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

Additional Data Will Be Collected Title of Presentation Client Along with each submission, data would be collected about the use of HPC and the computers used: --> How many CPU hours, how many core hours, total CPUs used, length of time for the job run, number of interactions ran, people involved, etc. --> OEM of the computer, OEM of the processors, OEM of the OS and middleware and applications, OEM of the interconnects and Storage Price (or price band) of the system would also be critical to collect Total amount invested in HPC to obtain the results Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

Implementation Plan Ideas: Timing Title of Presentation Client Launch the concept and plan at the September HPC User Forum Target SC10 for the official announcement of the program – and ask for submissions Target the next ISC to announce the first awards Or a timing that works well for the press partner Copyright 2007 IDC. Reproduction is forbidden unless authorized. All rights reserved.

Questions? Please email: hpc@idc.com Or check out: www.hpcuserforum.com