Coping with Variability in Semiconductor Manufacturing Costas J. Spanos Berkeley Computer Aided Manufacturing Department of EECS University of California, Berkeley 12/6/04 Costas J. Spanos 9/16/2018

The Traditional Semiconductor Manufacturing Environment IC Design Mead & Conway “design rules” Manufacturing Process Development Costas J. Spanos 9/16/2018

Introduction Error budgets cannot keep up with shrinking dimensions. In the sub-100nm generations, Critical Dimensions (CDs) are hard to control. Typical problem: manufacture 65nm features, and try to keep error at +/- ~5nm. Most of the time, one can only measure those features with +/- 2nm precision! Costas J. Spanos 9/16/2018

The objective is to maintain both Wafer to Wafer and Across Wafer CD Uniformity Bad Good Costas J. Spanos 9/16/2018

Outline Measuring Variability Controlling Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with an emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process Costas J. Spanos 9/16/2018

Sources of CD Variation Exposure: Across-Field PEB: Across-Wafer Spin/Coat: Across-Wafer Total CD Variation Develop: Across-Wafer Deposition: Across-Wafer Across-Lot Etch: Across-Wafer Systematic CD variation components with different frequencies are combined. Costas J. Spanos 9/16/2018

What was the state of the wafer during processing? Processing Sequence processing equipment wafers to be processed finished wafer What was the state of the wafer during processing? Costas J. Spanos 9/16/2018

Smart Sensor Wafers In situ sensor array, with integrated power and telemetry Applications: process control, calibration, diagnostics & monitoring, process design Costas J. Spanos 9/16/2018

The Approach processing equipment SensorWafer feedback data process control wafers to be processed base station Costas J. Spanos 9/16/2018

1998: Off-the-shelf Components, Ni on Al, Solder Paste Mount… thermistor resistor capacitors PIC voltage regulator LED batteries 100mm Costas J. Spanos 9/16/2018

Today: The Sensor Wafer SiO2 polyimid HAND OUT THE WAFER FOR THE AUDIENCE TO PASS AROUND Wafers are built on standard silicon oxide coated substrates, the module has a low enough profile (4.5mm) to allow for full cassette to cassette transport on most major tools. (if they ask about their particular equipment, OnWafer has a database of tested equipment and also we can supply the mousetrap wafer – go to appendix slide by pressing the arrow button, bottom right of screen) The sensors are coated with an inert polyimid. The module contains the logic and memory and is encapsulated in polycarbonate The unit is limited by the battery life which delivers approximately 100 hours at 130 degrees The wafer can be directly loaded into the wafer cassette module Courtesy OnWafer Technologies Costas J. Spanos 9/16/2018

Much more than you ever wanted to know about Post Exposure Bake Overshoot Steady Heating Cooling 200mm ArF 90nm 130oC 60sec Chill Courtesy OnWafer Technologies Costas J. Spanos 9/16/2018

On-Wafer Plasma Monitoring 200mm Poly Etching Routine He Reduced He main etch pre-etch over etch de-chuck This shows results from a typical polysilicon etch. The results show all the steps of the process. The main etch where the majority of the polysilicon is removed, The over etch where it backs down in power And the de-chuck, interestingly this is the hottest. Now, this is meaningless for the product as there is no processing, but if you are currently using a technology known as temp dots where you mount them on a test wafer, you will be measuring this maximum temperature, missing the temperature of the important etch steps Having this capability means you can rapidly run experiments in minutes that previously would have taken days. Here we wanted to adjust helium pressures to optimize uniformity, from the 3D plot on the right, you can see with the lower pressure, we had substantial edge heating. When you do not have to open the chamber or measure wafers, this type of “what if” analysis can be performed in minutes Costas J. Spanos 9/16/2018

Cool chuck - 200mm Poly Etching main etch Temperature fluctuations during main etch This is an example of running a low temperature chuck, you can see the main etch step and notice our sensors are fast enough to see the fluctuations in the chiller Again the de chuck stage is the hottest operation Costas J. Spanos 9/16/2018

Can see rotating magnetic field ! phase delay in temp fluctuation Can calculate B-field period Can see rotation is clockwise Costas J. Spanos 9/16/2018

Photo-/RF Transmitter Next Step: Zero-Footprint Metrology Wafer Data Transmission Photo-/RF Transmitter Data Processing, Storage Unit Dielectric Layer Si Battery Data Acquisition Unit 500m Prototyping a zero-footprint metrology wafer with optical detection unit and encapsulated power source. Costas J. Spanos 9/16/2018

Proposed Architecture Power Management & RF Transmission Unit Self-contained wireless transmitter + - + - Measurement Units Power Integrated excitation/detection Unit Thin film Battery Power Unit Costas J. Spanos 9/16/2018

3 x 3 Pixels Optical Metrology Prototype Bottom Wafer with LED Photodetector integrated Top Wafer Costas J. Spanos 9/16/2018

Feasibility Test: Thickness Measurement 5mm Green LED Blue LED Shipley S1818 PR on Glass Slide LED PD Si Packaging Substrate Glass Slide Test Coating Filter Costas J. Spanos 9/16/2018

Wireless Aerial Image Metrology Mask light Image system Wafer Mask image NA Partial coherence Illumination aberrations Defocus magnification Aerial image Latent image Resist image Costas J. Spanos 9/16/2018

An Integrated Aerial Image Sensor Dark contact mask forms a “moving” aperture to capture incident electromagnetic field. Poly-silicon mask Substrate Photo- detector Mask aperture How can a mm detector retrieve nanometer-scale resolution of the aerial image? Φ1 Φ2 Φ3 p-Si Costas J. Spanos 9/16/2018

Moiré Patterns for Spatial Frequency Shift Narrow CD Patterns Overlap Pattern rotates 4o Pattern rotates 8o Pattern rotates 16o Wide CD Costas J. Spanos 9/16/2018

Aperture pattern shift testing Image pattern Detect pattern 4.4 2.2 2 d Detector mask layout design Mask layout Measurement result Costas J. Spanos 9/16/2018

Near-Field Optical Simulation mask Intensity at the center of the simulation domain Costas J. Spanos 9/16/2018

Outline Measuring Variability Controlling Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with an emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process Costas J. Spanos 9/16/2018

Manufacturing Evolution… Model & Controller RT equipment model Diagnostic Engine Costas J. Spanos 9/16/2018

Advanced Process Control Post-Process Measurements Automatic Fault Detection Summarized In-Situ Measurements In-Situ Sensors (to next tool) (from Previous tool) Real Time Equipment Controller Run to Run Controller Equipment State Process State Wafer State Metrology Post-Process Measurements For Feed- forward Control Process Model Equipment Model Updated Recipe Modified Recipe Drift Noise Courtesy AMD Costas J. Spanos 9/16/2018

Factory Wide Control with Real-Time Optimization Courtesy AMD Costas J. Spanos 9/16/2018

APC Applications A B D C Courtesy Intel APC Proposed Apps (28) Etch C4 Control Points APC Proposed Apps (28) Completed Proposed 14 12 Etch C4 10 2 3 Litho 8 # of Apps 6 10 4 2 Polish CD Reg Thickness 6 Control Points D C TF/Diff Courtesy Intel 7 Costas J. Spanos 9/16/2018

Post Exposure Bake Track Equipment Complexity is Increasing 10 Years of Product Evolution Multi-Zone Control Single Zone Control PEB Evolved from a Single Zone to Multi-Zone Control System Why? Costas J. Spanos 9/16/2018

PEB Hotplate Thermal Profile Optimization System Plate Type Specific Thermal Profile Modeling Engine AutoCal™ Input Offset Values Optimized for Both Within-Plate and Plate-to-Plate Thermal Profile Uniformities Offset Generator Engine Output Input Baseline Thermal Profile Condition BakeTemp™ & OnView™ OnWafer Technologies Costas J. Spanos 9/16/2018

PEB Temp Control Before After 2.700oC 0.175oC 16 plates, 120 ºC Target Target = 120oC 2.700oC 0.175oC 16 plates, 120 ºC Target OnWafer Technologies Costas J. Spanos 9/16/2018

Spatial PEB/CD Distribution Correlation Costas J. Spanos 9/16/2018

PEB Hotplate Critical Dimension Optimization System AutoCal™ AutoCD™ Plate Type Specific Thermal Profile Modeling Engine Resist & Litho Cell Specific CD Modeling Engine Input Input Offset Values Optimized for Both Within-Plate and Plate-to-Plate Critical Dimensions Uniformities Offset Generator Engine Output Input Input Baseline Thermal Profile Condition Baseline CD Profiles per Plate Customer Provided BakeTemp™ & OnView™ OnWafer Technologies Costas J. Spanos 9/16/2018

CDU Improvement OnWafer Technologies Costas J. Spanos 9/16/2018

Poor Across-Wafer CD Uniformity The New Problem How can we improve the across-wafer CDU? How much can we improve CDU? Poor Across-Wafer CD Uniformity Processing Tool Etch Wafer Litho Costas J. Spanos 9/16/2018

Supervisory Control with Wireless Metrology Compensate for systematic spatial non-uniformities across the litho-etch sequence using all available control authority: Exposure step: die to die dose PEB step: temperature of multi-zone bake plate Etch: backside pressure of dual-zone He chuck Exposure PEB / Develop Etch Wafer-level CD Metrology Optimizer Scatterometry/CDSEM dose temperature He pressure Costas J. Spanos 9/16/2018

Present Status of “Active” CD Control Exposure Etch PA Bake PEB Poly Etch System Photoresist Removal Etch Etch Spin Develop PD Bake HMDS ADI AEI ELM Costas J. Spanos 9/16/2018

On-wafer and in-line metrology in pattern transfer I (x, y) T (t, x, y) V (t, x, y) E (t, x, y) … Exposure T (t, x, y) Etch PA Bake PEB Poly Etch System Photoresist Removal Etch Etch Thin Film Develop Spin OCD OCD PD Bake HMDS OCD ELM Costas J. Spanos 9/16/2018

CDU control has to incorporate many strategies I (x, y) Optimal Pattern Design T (t, x, y) V (t, x, y) E (t, x, y) FF/FB Control, chuck diagnostics Exposure T (t, x, y) FF control Etch PA Bake PEB Poly Etch System Photoresist Removal Etch Etch Thin Film FB/FF Control Develop Spin OCD FB Control OCD FB/FF Control PD Bake HMDS OCD Profile Inversion FB Control ELM Costas J. Spanos 9/16/2018

Outline Measuring Variability Controlling Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with an emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process Costas J. Spanos 9/16/2018

Spatial Correlation Analysis Exhaustive poly-CD measurements (280/field): Costas J. Spanos 9/16/2018

Origin of Spatial Correlation Dependence - - Average Wafer Scaled Mask Errors Across-Field Systematic Variation = Across-Wafer Systematic Variation Polynomial Model Costas J. Spanos 9/16/2018

Origin of Spatial Correlation Dependence Within-die variation: Average Field Scan Slit Scaled Mask Errors Non-mask related across-field systematic variation - = Polynomial model of across-field systematic variation The “shape” of this model will be very similar to the “shape” of spatial correlation dependence. Costas J. Spanos 9/16/2018

Origin of Spatial Correlation Dependence By slicing the within-die variation, we can see where the origin of the spatial correlation plots Costas J. Spanos 9/16/2018

Spatial Correlation Model Fit rudimentary linear model to spatial correlation curve extracted from empirical data: Ignore this part - distances to large for typical IC sub-circuit rB Characteristic “correlation baseline” XL, characteristic “correlation length” Costas J. Spanos 9/16/2018

Origin of Spatial Correlation Dependence The across-wafer variation impacts rB: Relative “weights” of field & wafer variation determine overall shape of spatial correlation curve Costas J. Spanos 9/16/2018

Calculation of Expected Effect Assuming n independent random variables with equal mean and variance, the variance of the sum of the n variables is: For  = 1, tot = nindv For  = 0, tot = n1/2indv Total potential improvement is factor of n1/2 (i.e., for a 16-stage path, maximum total delay variation reduction is ~4x…) Costas J. Spanos 9/16/2018

Monte Carlo Simulations Use canonical circuit of FO2 NAND-chain w/ stages separated by 100mm local interconnect, ST 90nm model: Perform Monte Carlo simulations for various combinations of XL, rB, and s/m (gate length variation) Measure resulting circuit delays, extract normalized delay variation (3s/m ) Input 100m Output Stage i 100 mm Costas J. Spanos 9/16/2018

Statistical Theory vs. Circuit Simulation Prediction of potential impact of spatial correlation using SPICE simulations on simple inverter chain: Costas J. Spanos 9/16/2018

Delay Variability vs. XL, rB, s/m Scaling gate length variation directly has most impact Reducing spatial correlation also reduces variability Normalized delay variability (3/) (%) Scaling factor B = 0.2 B = 0.0 B = 0.4 0% 20% 40% 60% 80% 100% XL scaling L scaling 25 20 15 10 5 Costas J. Spanos 9/16/2018

Outline Measuring Variability Controlling Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with en emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process Costas J. Spanos 9/16/2018

Coping with Variability in Semiconductor Manufacturing Robust Designs IC Design Novel Metrology / APC Manufacturing Process Development Error Budget Engineering Design for Controllability Costas J. Spanos 9/16/2018