Software Defined Radio Transceiver Implementation A Single Semester Software Defined Radio Transceiver Implementation In a Xilinx Spartant-3 FPGA Steven Brown Justin Ford Kyusun Choi Penn State University 9/17/2018 Sp06 CSE598a/EE597g Choi

SDR Technology Commercial AM and FM radio TV Walkie Talkie Cell phone Cordless phone Garage door opener Car door opener WiFi/802.11 GPS Shortwave radio Remote control car/toy 9/17/2018 Sp06 CSE598a/EE597g Choi Image source: http://www.target.com

SDR Technology Military Image source: http://www.deutschdao.com/ http://www.nu-cast.com/ http://www2.hawaii.edu/~mcgraw/Page-Military/Military-Navy/carrier-1.jpg http://www.mathworks.com http://www.shopingathome.com/Military%20Wireless.htm 9/17/2018 Sp06 CSE598a/EE597g Choi

Hardware Architecture 9/17/2018 Sp06 CSE598a/EE597g Choi

SOFTWARE DEFINED RADIO IN AN FPGA OPERATING AT CARRIER FREQUENCY 9/17/2018 Sp06 CSE598a/EE597g Choi

Filter Design + 1 / Z G + + 9/17/2018 Sp06 CSE598a/EE597g Choi Considered Algorithms / Selected Algorithm Though only 6-bit results are shown here, the algorithms were simulated with up to 10 bits of mantissa. The number of exponent bits was not as significant to the quality of the results. 50 100 150 200 250 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 freq (MHz) L e v l ( d B ) All-Pass Coupled Std. Direct Lattice Zero-Free Direct 6-bit Mantissa Frequency Response Filter Stucture # Add # Mult Worst case latency Std. Direct 3 2× ADLAT + 1× MULAT All - pass 7 2 4× + 2× Lattice 4 3× Coupled 5 Zero Free Direct Zero-free Direct 1 / Z x [ n ] - a 2 G y + + 1 / Z v y [ n ] - x h G Coupled + 1/Z -a1 -a2 G y[n] x[n] - Standard Direct + 1/Z - A B x[n] y[n] All Pass Lattice - k 1 x [ n ] y / Z 2 + G 9/17/2018 Sp06 CSE598a/EE597g Choi

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Applications: Ultrasound Microscope Ultrasound Endoscope Ultrasound Pill-camera Ultrasound pill-camera complements the photo pill-camera by providing the following advantages: Imaging below the tissues Imaging even in murky liquids Imaging without illumination Remote medical practice Soldiers – Military Astronauts - NASA 9/17/2018 Sp06 CSE598a/EE597g Choi

Applications: Ultrasound Microscope More ideas: Ultrasound communication instead of RF communication for the image transmission Use lower frequency ultrasound actuation for positioning control and propulsion Add lab-on-a-chip for fluid chemical analysis Add drug dispenser, temperature sensor, other micro equipments (micro piezo actuators) in the pill 9/17/2018 Sp06 CSE598a/EE597g Choi

A Novel Scanning Acoustic Microscopy Acoustic Lens Y X Computer Monitor Z Stage Culture Liquid Cell Temperature Controlled Chamber X-Y Stage Control Board 2-D Transducer Array Front-end Board 9/17/2018 Sp06 CSE598a/EE597g Choi

A Novel Scanning Acoustic Microscopy 9/17/2018 Sp06 CSE598a/EE597g Choi

Block Diagram of the first prototype CMOS Chip Control & IO Address Decoder Command Host Computer AWG Tx Driver Transducers VGA SRAM (27kbyte) ADC 16bit On-chip Self-test Circuitry The Front-end Chip 2bit 5bit Variable Delay Channel Selection Rx Preamp Analog Signal Processing Part (9 Channels) 9ch Controller: controls the RF chip and interfaces Host computer with the chip. Tx Driver: Generates 50 MHz signal to be sent to the transducers. Preamp: Standard preamp design that is interfaced to the Rx side. VGA: Variable Gain Amplifier. This will be utilized to achieve the 30 – 80 dB boost. ADC: Analog to Digital Converter. In this configuration there are 9 ADCs, each one dedicated to an individual RF channel. SRAM: Analog to Digital Converter output data will be saved at SRAM. Then the data will be transferred to the host DSP processor. 9/17/2018 Sp06 CSE598a/EE597g Choi

Functional Diagram of the CMOS Chip SRAM ADC Preamp/VGA Channel <0> Channel <n> Channel <i> HOST Computer Ctrl Command (Ex.) Tx. Pulse Gen Timer Data tmin count Ch<0:n> (Read) Transducer Array ASIC Chip Fire Receive Preamp Output VGA Output RF Front-End tmin Reflection Signal from Transducers Excitation Pulse (50MHz) Functional diagram of the CMOS chip: When this chip sends out excitation pulse to transducers, transducers convert electrical signal to ultrasonic wave. Then ultrasonic wave is reflected by the object of interest, and captured by the transducer array. The received signal from the transducer is then fed to the preamp on the CMOS chip. The reflected ultrasound signal from the shallower depth will be received as strong signal; however, the reflected ultrasound signal from the deeper depth will be received as weak signal. Therefore, Variable Gain Amplifier should provide needed gain boost for the reflected ultrasound signal from deeper depth. The time varying control signal is applied to VGA gain control input such that the signal strength at the VGA output is constant over time (depth). The amplified analog signal is converted to digital signal by ADC, and the digital signal is stored on SRAM for further image process. time 9/17/2018 Sp06 CSE598a/EE597g Choi

Simplified Block Diagram of the Chip (1 channel) Control & DSP Tx Generator Transducer Array VGA SRAM (3k byte) A/D Converter Tx Driver Programmable Delay Preamp Custom Designed IC Simplified block diagram of the front-end chip: Actual Chip contains 9 channels rather than the 1 channel shown here. (Use this diagram for papers) 9/17/2018 Sp06 CSE598a/EE597g Choi

Pin Configuration SRAM Control Analog Circuits Total: 64ea Transducer: 9ea Control: 2ea Address: 5ea Date Out: 16ea Power: 16ea Clock: 2ea VGA Monitor: 9ea ETC: 5ea Total: 64ea 9/17/2018 Sp06 CSE598a/EE597g Choi

Layout of the full-custom designed CMOS Chip Analog Components (Preamp, VGA, ADC, Tx Driver) Control Circuits SRAM 5006 um 5360 um Area: 26.83um2 9/17/2018 Sp06 CSE598a/EE597g Choi

Specifications of the CMOS Chip On-chip Memory SRAM Capacity: 3k byte/Channel Speed: up to 125 MHz Number of Bits: 16 bit Operating Functions Single Channel Mode Multiple Channel Mode Power Supply 3.3V Fabrication Information Chip Size: 26.83mm2 Package: LQFP 64pin Design Rule: TSMC 0.35um (2 poly 4 metal) Beam-former Frequency: 100 MHz (5 more options b/w 3.9MHz to 125MHz) Pulse Type: Sine/Square wave Amplitude of Pulse: 3.3V Number of Channels 9 Channels Preamp Gain: 1.8 ~ 8.6 (Adjustable) Bandwidth: 600 MHz@5dB ~ 52 MHz@19dB VGA Gain: -5dB to 15dB Bandwidth: 300 MHz A/D Converter Type: Pipelined Algorithmic ADC Resolution: 8 bit Sampling Rate: 250 MS/s 9/17/2018 Sp06 CSE598a/EE597g Choi

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