EE 5340 Semiconductor Device Theory Lecture 7 - Fall 2010 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc
Second Assignment Please print and bring to class a signed copy of the document appearing at http://www.uta.edu/ee/COE%20Ethics%20Statement%20Fall%2007.pdf L07 13Sep10
Silicon Planar Process1 M&K1 Fig. 2.1 Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) oxide removal, (c) deposition of dopant atoms, (d) diffusion of dopant atoms into exposed regions of silicon. L07 13Sep10
LOCOS Process1 1Fig 2.26 LOCal Oxidation of Silicon (LOCOS). (a) Defined pattern consisting of stress-relief oxide and Si3N4 where further oxidation is not desired, (b) thick oxide layer grown over the bare silicon region, (c) stress-relief oxide and Si3N4 removed by etching, (d) scanning electron micrograph (5000 X) showing LOCOS-processed wafer at (b). L07 13Sep10
Al Interconnects1 1Figure 2.33 (p. 104) A thin layer of aluminum can be used to connect various doped regions of a semiconductor device. 1 L07 13Sep10
Ion Implantation1 1Figure 2.15 (p. 80) In ion implantation, a beam of high-energy ions strikes selected regions of the semiconductor surface, penetrating into these exposed regions. L07 13Sep10
Phosphorous implant Range (M&K1 Figure 2 Phosphorous implant Range (M&K1 Figure 2.17) Projected range Rp and its standard devia-tion DRp for implantation of phosphorus into Si, SiO2, Si3N4, and Al [M&K ref 11]. L07 13Sep10
Implant and Diffusion Profiles Figure 2.211 Complementary-error-function and Gaussian distribu-tions; the vertical axis is normalized to the peak con-centration Cs, while the horizon-tal axis is normal-ized to the char-acteristic length L07 13Sep10
Diffused or Implanted IC Resistor (Fig 2.451) L07 13Sep10
An IC Resistor with L = 8W (M&K)1 L07 13Sep10
Typical IC doping profile (M&K Fig. 2.441) L07 13Sep10
Mobilities** L07 13Sep10
IC Resistor Conductance L07 13Sep10
An IC Resistor with Ns = 8, R = 8Rs (M&K)1 L07 13Sep10
The effect of lateral diffusion (M&K1) L07 13Sep10
A serpentine pattern IC Resistor (M&K1) R = NSRS + 0.65NCRS note: RC = 0.65RS L07 13Sep10
References 1 and M&KDevice Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, 1986. See Semiconductor Device Fundamentals, by Pierret, Addison-Wesley, 1996, for another treatment of the m model. 2Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, 1981. 3Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, 1997. L07 13Sep10