RTL Design Methodology Lecture 8 RTL Design Methodology MIN_MAX_AVR Example

Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 6, FSMD S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 10.2, Design Examples ECE 448 – FPGA and ASIC Design with VHDL

Structure of a Typical Digital System Data Inputs Control Inputs Control Signals Datapath (Execution Unit) Controller (Control Unit) Status Signals Data Outputs Control Outputs

Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block diagram Block diagram State diagram or ASM chart VHDL code VHDL code VHDL code

Steps of the Design Process Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller ASM chart of the Controller RTL VHDL code Testbench Debugging Synthesis and implementation Experimental testing

Steps of the Design Process Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller ASM chart of the Controller RTL VHDL code Testbench Debugging Synthesis and implementation Experimental testing

MIN_MAX_AVR Example

Circuit Interface clk DONE reset n n in_data out_data 5 MIN_MAX_AVR in_addr 2 out_addr write START

Interface Table Port Width Meaning clk 1 System clock reset System reset – clears internal registers in_data n Input data bus in_addr 5 Address of the internal memory where input data is stored write Synchronous write control signal START Starts the computations DONE Asserted when all results are ready out_data Output data bus used to read results out_addr 2 01 – reading minimum 10 – reading maximum 11 – reading average