2nd Data Prefetching Championship Results and Awards

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Presentation transcript:

2nd Data Prefetching Championship Results and Awards Seth Pugsley

Thanks! Big thanks to Hyesoon Kim and the Program Committee Babak Falsafi Mike Ferdman Aamer Jaleel Daniel Jiménez Calvin Lin Moin Qureshi Eric Rotenberg Thomas Wenisch Thanks to Alaa Alameldeen and Chris Wilkerson at Intel Labs Thanks also to submission chair Hyojong Kim

DPC2Sim Parameters Single Core - 3.2 GHz, 6-wide, 256 ROB 3 level cache hierarchy 16 KB L1D, 128 KB L2, 1 MB L3 1 channel 64-bit 1600 MT/s DDR3 channel Prefetching all done at the L2 level L2 read event is the entry point into the prefetcher Prefetches inserted into the L2 read queue void l2_prefetcher_operate(cpu_num, addr, PC, cache_hit); MSHR, read queue occupancy, cycle time

Championship Scoring 4 configurations Score for each configuration Default (no knobs) Small LLC Low bandwidth Scrambled loads Score for each configuration Geomean((Prefetcher IPC) / (No prefetcher IPC)) Final score is sum of 4 scores (20 SPEC CPU 2006 workloads) x (3 traces/workload) x (1 B instructions/trace) x (4 configurations) = 240 B simulated instructions

Total Scores

Total Scores

Default Configuration Scores

Small LLC Scores

Low Bandwidth Scores

Scrambled Loads Scores

Effect of Scrambling Loads: IPC(scrambled)/IPC(default)

Idealized Total Score: Max(All Prefetchers)

Accepted Workshop Prefetchers Scores

Awards

Awards 3rd place - Prefetching On-time and When It Works Ibrahim Burak Karsli, Mustafa Cavus, and Resit Sendag

Awards 3rd place - Prefetching On-time and When It Works Ibrahim Burak Karsli, Mustafa Cavus, and Resit Sendag 2nd place - Towards Bandwidth-Efficient Prefetching with Slim AMPM Vinson Young and Ajit Krisshna

Awards 3rd place - Prefetching On-time and When It Works Ibrahim Burak Karsli, Mustafa Cavus, and Resit Sendag 2nd place - Towards Bandwidth-Efficient Prefetching with Slim AMPM Vinson Young and Ajit Krisshna 1st place - A Best-Offset Prefetcher Pierre Michaud

Thanks for participating!