Microcomputer & Interfacing Lecture 1 The 8086 Microprocessor BY: Tsegamlak Terefe 9/17/2018

Hardware Architecture Physical Address Generation Objective Hardware Architecture Physical Address Generation BY: Tsegamlak Terefe 9/17/2018

Architecture [Register Level] In general a microprocessor will have the following components ALU Registers Decoder & Fetcher Data & Address Bus The 8086 microprocessor have two major parts The Execution Unit The Bus Interface Unit Here are some registers you will find in any microprocessor based systems PC (Program Counter) IR(Instruction Register) SP (Stack Pointer) FR (Flag Registers) GPIO (General purpose I/O Registers) AC (Accumulator) BY: Tsegamlak Terefe 9/17/2018

Architecture [Register Level] 40 pins 16-bit architecture Clock Rate : 5Mhz- 10MHz max 20 bit address bus In microprocessors the more physical pins you have the more functionality you will add to your system and the more components you can interface with it. In addition to this You might have heard that operating systems in computers as 32bit, 64bit this will tell you that your CPU will have 32bit or 64bit data bus. And note that a 64 bit data buss might operate as 32bit system but the vice versa might not be true. BY: Tsegamlak Terefe 9/17/2018

Architecture [Register Level] BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) The Execution unit have the following components ALU (Arithmetic & Logic Unit) 16 bit Decoder Registers Control Circuitry ALU: Performs Arithmetic and Logical operations. Control Circuitry : Controls flow of operations Decoder : Interprets instruction fetched from memory and activate/ deactivate necessary components for the ALU to perform its action. Note: The ALU can also operate as an 8 bit. BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) Registers: The EU have various registers to hold temporary data, offset to an address & status of various operations. Here are the list of registers within the EU. BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) Accumulator(AX): 16 bit general purpose register which can be used for multiplication, division, adjustment instruction, I/0 or hold temporary value. Base Index (BX): 16 bit register which is used to hold temporary value or offset address to memory location. Count (CX): 16 bit register which is used to hold temporary value or count value for loop instructions. Data (DX): 16 bit register which is used to hold the result of multiplication , part of dividend before division ,temporary data and port address for I/O. BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) The above registers can operate in 16 bit or 8 bit mode. The 8 bit respective value will be AX=>AH+AL, BX=>BH+BL, CX=>CH+CL, DX=>DH+DL AX,BX,CX,DX Note: if you want to access only the 8 bits you can address them as AL,BL,CL,DL,AH,BH,CH,DH. In this case only the selected 8 bits will be affected due to the operation you performed. 16 AH,BH,CH,DH AL,BL,CL,DL 8 8 BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) Destination Index (DI): A 16 bit register containing destination address offset of string instructions. Source Index (SI) : A 16 bit register containing Source address offset of string instructions. Base Pointer (BP): A 16 bit register containing an offset that points to memory location (stack). Stack Pointer (SP): A 16 bit register containing an offset that points to a memory location called Stack. Note: This registers can not be accessed as an eight bit register. instructions performed on them will update the whole register . BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) Flags : Flags indicate conditions of the processor and control its operations. The flag contains 8 used bits with each bit representing a certain condition. . BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) Carry bit (C) : This bit will be set if there is a carry out of most significant bit in unsigned addition or a borrow in unsigned subtraction. Parity (P) : This bit will be set if the lower bytes of a result contains an even number of ones. Auxiliary Carry (AC) : This bit will be set if there is a carry out or borrow from the lower nibble of addition and subtraction respectively. . BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) Zero (Z) : This bit will be set if an instruction results a zero. Sign flag (S) : This bit will be set if an arithmetic operation results in a negative value. Over flow (O) : This bit will be set if an instruction produce a result that can not be held by the available registers. . BY: Tsegamlak Terefe 9/17/2018

The Execution Unit (EU) Interrupt (I) : This bit will be set if the processor acknowledges a makeable interrupt. Direction (D) : If set strings are processed from higher to lower bit other wise they are processed from low to higher bit. . BY: Tsegamlak Terefe 9/17/2018

The Bus Interface Unit (BIU) . BY: Tsegamlak Terefe 9/17/2018

The Bus Interface Unit (BIU) The BIU have the main functionality of fetching instructions and generating addresses. The BIU unit is capable of fetching up to six instructions in its FIFO queue . This is done while the EU is decoding and executing instruction i.e. where the EU is not using the BUS. Hence when the EU finishes the execution of the current instruction it will simply fetch the next instruction if the current executed instruction dose not require a branch or jump (control transfer instruction in general). . BY: Tsegamlak Terefe 9/17/2018

The Bus Interface Unit (BIU) Registers Code Segment (CS) Data Segment (DS) Extra Segment (ES) Stack Segment (SS) 20 bit address Bus which can address in a range of 1MB memory. . 8086 Memory 20-bit Address 16-bit Data BY: Tsegamlak Terefe 9/17/2018

The Bus Interface Unit (BIU) 8086 will support 1MB memory which is divided into 64KBs of segments for various purposes. .Hence Memory is addressed as Segment Registers + offset registers=Memory Address BY: Tsegamlak Terefe 9/17/2018

Note: This dose not mean that you have to segment your memory exactly like the picture it is just an example. The allocation of the memory segments to the four types completely depends on the choice of the programmer. BY: Tsegamlak Terefe 9/17/2018

How is address generated ? As mentioned earlier address is generated with the use of segment and offset registers. Which segment is pointing to where ? Code segment (CS): This segment register is pointing to a memory segment containing code (instruction). Data segment (DS) : This segment register is pointing to a memory segment containing Data. Note: The segment registers are a 16 bit registers hence can not be accessed as xl,xh. Any operation performed on them will affect the whole register. BY: Tsegamlak Terefe 9/17/2018

How is address generated ? As mentioned earlier address is generated with the use of segment and offset registers. Stack Segment (SS): This register points to a segment used as stack. Stacks are memory locations where addresses and data are stored while a sub program is being executed. Extra segment (ES) : This register points to a segment where destination data could be stored in string manipulation instruction. BY: Tsegamlak Terefe 9/17/2018

How is address generated ? Segment Registers are shifted by four bits/ nibble to the left . The value at the offset register is added to the shifted value in the segment register. (D,E,S,C)S<<4 + offset register => 20 bit memory address BY: Tsegamlak Terefe 9/17/2018

How is address generated ? E.g. If the segment address is 1005h and the offset is 5555h, then the physical address is calculated as follows Segment address --------- 1005h Offset address------------- 5555h Segment address--------- 1005h --------- 0001 0000 0000 0101 Shifted by 4 bit positions---------- 0001 0000 0000 0101 0000 Offset address----------------------- + 0101 0101 0101 0101 Physical address ------------------- 0001 0101 0101 1010 0101 1 5 5 A 5 h BY: Tsegamlak Terefe 9/17/2018

How is address generated ? BY: Tsegamlak Terefe 9/17/2018

Offsets Each segment register is associated with its corresponding offset register. CS:IP: The pair of code segment and Instruction pointer will indicate the next instruction to be fetched. Here the CS will indicate the base address (starting address)of the code in memory while IP will point the offset from the base address. E.g. CS:IP=>348A:4214 => 348A0+4214=38AB4 Note: BY: Tsegamlak Terefe 9/17/2018

Offsets SS:SP/BP:-These pair will indicate the base address of the stack segment and the offset from the base address respectively. DS: SI/BX/DI :- These pairs will indicate the base address of the data segment and the offset from the base address respectively. Note: BY: Tsegamlak Terefe 9/17/2018

Summary Note: BY: Tsegamlak Terefe 9/17/2018

Summary Note: BY: Tsegamlak Terefe 9/17/2018

Dr. Manoj handout chapter one Summary For further reference Dr. Manoj handout chapter one For testing EMU8086 Note: BY: Tsegamlak Terefe 9/17/2018

Pin outs Interfacing the 8086 Next Lecture Pin outs Interfacing the 8086 Note: BY: Tsegamlak Terefe 9/17/2018