Lecture Note 5 Computer Arithmetic Pradondet Nilagupta (based on lecture note of Prof J. Kelly Flanagan)

Computer Arithmetic This lecture will introduce basic number representations and introduce basic integer and floating point arithmetic.

Number Representation Any number can be represented in any base by the simple sum of each digit's value, positional notation: d * basei The value 1011 (binary) equals 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11 (decimal).

Number Representation as a 32 bit number this would be represented as follows: 0000 0000 0000 0000 0000 0000 0000 1011 The most significant bit (MSB) is on the left and the least significant bit (LSB) is on the right. In the number above, the LSB is called bit 0 and the MSB is called bit 31.

Range of Values With 32 bits it is possible to have unsigned numbers that range from 0 to 232 - 1 = 4,294,967,295. This is quite reasonable for address calculations of present machines, but future machines will surely have more than 232 memory locations. In addition to more memory it is highly useful to be able to represent negative as well as positive integers and numbers smaller and larger then those possible with this format.

Signed Integers Since in the binary number system we have an even number of unique representations for a given number of bits we have two choices: 1. Have a balanced system with the same number of negative and positive values, but what about zero? If we represent zero we have an odd number of values to represent. This can be done by allowing zero to be represented by two different bit patterns.

Signed Integers 2. Have an unbalanced system where zero has one representation, but there is either an extra positive or negative value. We would like a balanced system, but this would require two different representations for the value zero. This evil (having two zeros) is better to avoid and not worth the benefits of having a balanced system. Consequently, an unbalanced system has been nearly universally adopted.

One's Complement How can we represent negative and positive numbers in the binary system? The 1's complement number system using 32 bits has a range from -(2^31 -1) to +(2^31 - 1). Zero can be represented as either positive or negative. The two forms of zero are represented by 0000 0000 0000 0000 0000 0000 0000 0000 (all zeros) or 1111 1111 1111 1111 1111 1111 1111 1111 (all ones).

One's Complement A negative number is formed by representing its magnitude in normal, positive binary format and then inverting each bit. 8-bit examples: 1111 1110 = -1 1111 1111 = -0 0000 0000 = +0 0000 0001 = +1 Having two forms of zero is a problem, but arithmetic is simple.

Two's Complement The 2's complement number system using 32 bits has a range from -2^31 to 2^31 - 1. Zero has only one representation: all zeros, but there is one extra negative value. Negative numbers always have the MSB set to 1 -- thus making sign detection extremely simple. Converting 2's complement numbers to signed decimal is extremely simple.

Example 2’s complement Convert 1011 1010 to signed decimal. 1 * -27 + 0 * 26 + 1 * 25 + 1 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 0 * 20 = -128 + 0 + 32 + 16 + 8 + 0 + 2 + 0 = -70. This approach is not feasible in hardware due to speed considerations.

Two's Complement Shortcuts Negation in two's complement is accomplished by inverting each bit of the number and then adding one to the result. Example: Convert -70 (decimal) to two's complement binary. |-70| = 70 = 0100 0110 (binary) ~ 0100 0110 = 1011 1001 (where ~ denotes bit inversion) 1011 1001 + 1 = 1011 1010 = -70 (2's comp).

Sign Extension To add a 16-bit value to a 32-bit value, the 16-bit value must first be sign extended. The two numbers are right aligned and the sign bit of the shorter number is replicated to the left until the two numbers are equal in length.

Example Sign Extension 0000 0000 0000 0000 0000 0000 0000 1011 + 1011 1010 we must sign extend the second number and then add: + 1111 1111 1111 1111 1111 1111 1011 1011 ------------------------------------------------------------- 1 1111 1111 1111 1111 1111 1111 1100 0101 The extra bit on the left is simply discarded, leaving us with 1111 1111 1111 1111 1111 1111 1100 0101 for our answer.

Integer Addition Straight forward approach consists of adding each bit together from right to left and propagating the carry from one bit to the next. Perform the operation 7 + 6 0111 + 0110 = 1101

Integer Addition Add the numbers 2,147,483,647 + 2 0111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0010 This is known as overflow Overflow can be handled in several ways An exception or interrupt can be asserted A bit in a status register can be set It can be completely ignored

Integer Subtraction Straight forward approach consists of negating one term and performing integer addition. Perform the operation 7 - 6 0111 - 0110 = 0001 Perform the operation 6 - 7 0110 - 0111 = 1111

Integer Subtraction Add the numbers -2,147,483,647 - 2 1000 0000 0000 0000 0000 0000 0000 0001 1111 1111 1111 1111 1111 1111 1111 1110 This is also overflow Overflow can be handled in several ways An exception or interrupt can be asserted A bit in a status register can be set It can be completely ignored

Integer Overflow Overflow can occur whenever the sum of two N bit numbers cannot be represented by another N bit number. Unsigned numbers must be treated differently than signed numbers. Unsigned numbers are usually used for address calculations and it is convenient to ignore overflow. In many architectures this is accomplished by having arithmetic instructions that ignore the overflow condition.

Longhand Multiplication Multiply 1000 * 1001 (either decimal or binary will work!) Multiplicand 1000 Multiplier 1001 1000 0000 ------- Product 1001000

Longhand Multiplication The first number is the multiplicand and the second the multiplier. The result is larger than either the multiplicand or the multiplier. If the size of the multiplicand is N bits and the size of the multiplier is M bits then the result is M+N bits long.

Simple Multiplication Algorithm The Multiplicand is stored in a 64 bit register and the Multiplier is stored in a 32 bit register while the product register is 64 bits long and initialized to zero. Test bit 0 of the multiplier If this bit is 0 Continue If this bit is 1 Add the multiplicand to the product and store back in the product register Shift the multiplicand register left 1 bit Shift the multiplier register right 1 bit If this is the 32nd iteration END else continue

MULTIPLY HARDWARE Version 1 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Shift Left 64-bit Multiplicand Shift Right 32-bit Multiplier 64-bit ALU Write 64-bit Product Control

Multiply Algorithm Version 1 Start Multiply Algorithm Version 1 Multiplier0 = 1 Test Multiplier0 Multiplier0 = 0 1. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. M’ier: 0011 M’and: 0000 0010 P: 0000 0000 1a. 1=>P=P+Mcand M’ier: 0011 Mcand: 0000 0010 P: 0000 0010 2. Shl Mcand M’ier: 0011 Mcand: 0000 0100 P: 0000 0010 3. Shr M’ier M’ier: 0001 Mcand: 0000 0100 P: 0000 0010 1a. 1=>P=P+Mcand M’ier: 0001 Mcand: 0000 0100 P: 0000 0110 2. Shl Mcand M’ier: 0001 Mcand: 0000 1000 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0000 1000 P: 0000 0110 1. 0=>nop M’ier: 0000 Mcand: 0000 1000 P: 0000 0110 2. Shl Mcand M’ier: 0000 Mcand: 0001 0000 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0001 0000 P: 0000 0110 1. 0=>nop M’ier: 0000 Mcand: 0001 0000 P: 0000 0110 2. Shl Mcand M’ier: 0000 Mcand: 0010 0000 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0010 0000 P: 0000 0110 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

Try It Yourself, V1 4x4 bit Multiply, Version 1 Show each step for 5 x 11 = 55 Multiplier Multiplicand Product Operation 0101 0000 1011 0000 0000 initial load Any questions so far? Let’s take a 5-minute break. +5 = 50 min. (Y:30)

Solution, V1 5 x 11 = 55 Multiplier Multiplicand Product Operation 0101 0000 1011 0000 0000 initial load 0101 0000 0011 0000 1011 add 0010 0001 0110 0000 1011 shift 0010 0001 0110 0000 1011 no add 0001 0010 1100 0000 1011 shift 0001 0010 1100 0011 0111 add 0000 0101 1000 0011 0111 shift 0000 0101 1000 0011 0111 no add 0000 1011 0000 0011 0111 shift Any questions so far? Let’s take a 5-minute break. +5 = 50 min. (Y:30)

Observations on Multiply Version 1 1 clock per cycle --> 32 x 3 = 100 clocks per multiply Ratio of multiply frequency to add is 5:1 to 100:1 But remember Amdahl’s Law! 1/2 bits in multiplicand always 0 64-bit adder is wasted 0’s inserted in right side of multiplicand as shifted least significant bits of product never changed once formed Instead of shifting multiplicand to left, shift product to right?

A Better Multiplier In the previous algorithm half of the bits in the multiplicand register are zero and contain no needed information. This algorithm requires only a 32 bit ALU and multiplicand register If multiplier bit 0 = 0 Continue if multiplier bit 0 = 1 Add the multiplicand to the left half of the product register and store the result in the left half Shift the product and multiplier registers right 1 bit. If this is the 32nd iteration END otherwise continue

MULTIPLY HARDWARE Version 2 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg 32-bit Multiplicand 32-bit Multiplier Shift Right 32-bit ALU Shift Right 64-bit Product Control Write

Multiply Algorithm Version 2 Start Multiply Algorithm Version 2 Multiplier0 = 1 Test Multiplier0 Multiplier0 = 0 1. Add multiplicand to the left half of product & place the result in the left half of Product register 2. Shift the Product register right 1 bit. M’ier: 0011 Mcand: 0010 P: 0000 0000 1a. 1=>P=P+Mcand M’ier: 0011 Mcand: 0010 P: 0010 0000 2. Shr P M’ier: 0011 Mcand: 0010 P: 0001 0000 3. Shr M’ier M’ier: 0001 Mcand: 0010 P: 0001 0000 1a. 1=>P=P+Mcand M’ier: 0001 Mcand: 0010 P: 0011 0000 2. Shr P M’ier: 0001 Mcand: 0010 P: 0001 1000 3. Shr M’ier M’ier: 0000 Mcand: 0010 P: 0001 1000 1. 0=>nop M’ier: 0000 Mcand: 0010 P: 0001 1000 2. Shr P M’ier: 0000 Mcand: 0010 P: 0000 1100 3. Shr M’ier M’ier: 0000 Mcand: 0010 P: 0000 1100 1. 0=>nop M’ier: 0000 Mcand: 0010 P: 0000 1100 2. Shr P M’ier: 0000 Mcand: 0010 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0010 P: 0000 0110 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

Try It Yourself, V2 4x4 bit Multiply, Version 2 Show each step for 5 x 11 = 55 Multiplier Multiplicand Product Operation 0101 1011 0000 0000 initial load Any questions so far? Let’s take a 5-minute break. +5 = 50 min. (Y:30)

Solution, V2 5 x 11 = 55 Multiplier Multiplicand Product Operation 0101 1011 0000 0000 initial load 0101 1011 1011 0000 add 0010 1011 0101 1000 shift 0010 1011 0101 1000 no add 0001 1011 0010 1100 shift 0001 1011 1101 1100 add 0000 1011 0110 1100 shift 0000 1011 0110 1100 no add 0000 1011 0011 0111 shift Any questions so far? Let’s take a 5-minute break. +5 = 50 min. (Y:30)

Observations on Multiply Version 2 Right half of product register wastes space that exactly matches size of multiplier So put multiplier in right half of product register ?

Another Multiplier In the previous algorithm the lower bits of the product register are wasted and could be used to store the multiplier. If product bit 0 = 0 Continue if product bit 0 = 1 Add the multiplicand to the left half of the product register and store the result in the left half Shift the product register right 1 bit. If this is the 32nd iteration END otherwise continue

MULTIPLY HARDWARE Version 3 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product / Multiplier reg 32-bit Multiplicand 32-bit ALU Shift Right 64-bit Product / Multiplier Control Write

Multiply Algorithm Version 3 Start Product0 = 1 Test Product0 Product0 = 0 1. Add multiplicand to the left half of product & place the result in the left half of Product register 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

Try It Yourself, V3 4x4 bit Multiply, Version 3 Show each step for 5 x 11 = 55 Multiplicand Product / Multiplier Operation 1011 0000 0101 initial load Any questions so far? Let’s take a 5-minute break. +5 = 50 min. (Y:30)

Solution, V3 5 x 11 = 55 Multiplicand Product / Multiplier Operation 1011 0000 0101 initial load 1011 1011 0101 add 1011 0101 1010 shift 1011 0101 1010 no add 1011 0010 1101 shift 1011 1101 1101 add 1011 0110 1100 shift 1011 0110 1100 no add 1011 0011 0111 shift Any questions so far? Let’s take a 5-minute break. +5 = 50 min. (Y:30)

Observations on Multiply Version 3 2 steps per bit because Multiplier & Product combined MIPS registers Hi and Lo are left and right half of Product Gives us MIPS instruction MultU What about signed multiplication? easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) Booth’s Algorithm is more elegant way to multiply signed numbers using same hardware as before

Booth's Multiplier In the previous algorithms only unsigned numbers were dealt with. Booth's algorithm deals with signed numbers as well. If the current and previous bits are 00 -- no addition or subtraction 01 -- end of string of one's so add the multiplicand to the left half of the product 10 -- beginning of a string of one's so subtract the multiplicand from the left half of the product 11 -- middle of a set of one's no addition or subtraction Shift the product register right 1 bit. If this is the 32nd iteration END otherwise continue

Example of Booth's Algorithm 5 = 00101 x -3 = x 11101 ---- ------- Product 00000 11101 0 subtract and shift 11011 11101 0 11101 11110 1 add and shift 00010 11110 1 00001 01111 0 subtract and shift 11100 01111 0 11110 00111 1 shift only 11111 00011 1 shift only 11111 10001 1 result = 10001 = -01111 = -15 (base10)

Floating Point Numbers Although 2's complement numbers have been used for nearly 25 years, many floating point number representations were used up until about 1985. Different representations make it very difficult to transfer data from one machine to another. A standard was and is needed.

Reals and Floats Consider the following numbers: 3.1415926 2.718 0.000000001 = 1 * 109 3,155,760,000 = 3.15576 * 109 The first three numbers cannot be represented by binary integers for obvious reasons, and the fourth cannot because signed 32-bit values are not large enough.

Reals and Floats Binary numbers can also be represented in scientific notation. The general form of this is s 1.m * 10 ^ e (binary) where s is either + or - representing the sign of the number, m is a string of 1s and 0s representing the fractional part of the mantissa, and e is a + or - string of 1s and 0s representing an exponent, or the number's order of magnitude. Note that this is almost identical in form to standard decimal scientific notation, except that the 10 represents 2 (decimal), not 10 (decimal).

Single Precision Floating Point (FP) Numbers Current computer systems dictate that FP numbers must fit in 32- or 64-bit registers. 32-bit or single precision FP numbers are organized as follows: seee eeee emmm mmmm mmmm mmmm mmmm mmmm where s is the sign of the number, e represents the biased exponent, and m represents the mantissa. 32-bit values range in magnitude from 10-38 to 1038.

Double Precision Floating Point Numbers 64 bit double precision floating point numbers are organized as follows: The MSB is the sign bit The next 11 bits are the exponent The remaining 52 bits are the significand The range in magnitude is from 10-308 to 10308 The growth of significand and exponent is a compromise between accuracy and range.

Implied Normalization In the IEEE 754 floating point standard, a leading 1 in the significant is assumed. This increases the effective length of the significant in both single and double precision arithmetic Numbers are therefore represented by: (-1)S * (1.M) * 2E-127 where S is the sign, M is the significant and E is the exponent

Why IEEE 754? Example if(x == 0.0) y = 17.0 else y = z/x Can this cause a divide by zero error?

Why IEEE 754? In the CDC6600 the adder and subtractor examine 13 bits while the multiplier/divider only examines 12 bits. Very small x's cause a problem. Solution: if(1.0 * x == 0.0) CRAY overflow, Why? y = 17.0 else y = z/x

Floating Point Addition It should be clear that addition and subtraction are performed in a similar manner. The steps for adding two floating point numbers is as follows: 1.We must adjust the smaller number until its exponent matches that of the larger number. 2.We add the significands together and round 3.Then the result is normalized by shifting the significand left or right and adjusting the exponent. 4.The number must again be rounded

Floating Point Addition Add the numbers 0.5 and -0.4375 In normalized form 0.5 = 1.000*2-1 -0.4375 = -1.110*2-2 Shift the significand of the smaller number right until the exponents of the two numbers are the same and add the significands -0.111*2-1 + 1.000*2-1 = 0.001*2-1

Floating Point Addition Normalize the result 0.001*2-1 = 0.010*2-2 = 0.100*2-3 = 1.000*2-4 Round the result This result already fits in the 4 bit field and no rounding is needed.

Floating Point Addition Continued Shift the significand of the smaller number right until the exponents of the two numbers are the same and add the significands 1.61010*10-1 = 0.016110*101

Floating Point Addition Continued Round the significand = 0.01610*101 0.016*101 + 9.999*101 = 10.015*101 Normalize the result 10.015*101 = 1.0015*102 Round the result 1.00210*102

Floating Point Multiplication 1.Add the biased exponents and subtract off the bias. 2.Multiply the significands, this is an unsigned multiply 3.Normalize the product shifting it right and incrementing the exponent 4.Check for overflow or underflow 5.Round the significand 6.Check to see if it is still normalized 7.Set the sign bit to the appropriate value, this is simply the XOR of the initial two sign bits

More FP Multiplication 0.5 * -0.4375 1.000*2-1 -1.110*2-2 1.000*2-1 = 0 01111110 000........many more sig. bits -1.110*2-2 = 1 01111101 110.........many more sig. bits

More FP Multiplication Add exponents and subtract bias 01111110 + 01111101 ------------- 11111011 = 124 + 127 = 251 + 10000001 -------------- 01111100 = 251 - 127 = 124

More FP Multiplication Multiply the significands 1.000 x 1.110 ------- 0000 1000 1110000 = 1.110000 = -1.110*2-3 = 1 01111100 110.......many more sig. bits

Guard, Round, and Sticky Bits The guard and round bits are two bits to the right of the significand used for intermediate results. 2.56*100 + 2.34*102 = 0.0256*102 + 2.34*102 Guard bit holds 5 Round bit holds 6 Now we round using two digits, the guard and round digits 0 to 49 round down 51 to 99 round up 50+sticky round up else even

Guard, Round, and Sticky Bits We round up with a 56 = 2.37*102 Without guard and round bits we would have truncated the intermediate result and acquired = 2.36*102

Floating Point Division Don't fear we are not going to do anything in detail with division. The hardware and algorithms are quite similar to multiplication, but instead of using addition subtraction is used heavily.

Logical Operations There are several logical operations that are useful or needed on a computer system AND OR NAND NOR NOT or Invert XOR XNOR

Logical Operations These functions are usually used to test bits fields or patterns within a machine word. These are quite different than the logical operations used in statements like if((a = b) || (c == d)) if((a !=b) & & (c == d))

Time and Space If we are performing a 32 bit addition all of the inputs are known immediately, but we must wait for the carry to ripple the length of the adder. In an ancient VLSI adder I designed and simulated the time for the carry propagation was 7ns. This would result in a 32 bit add time of 224ns resulting in a usable system clock rate of 4.46MHz. This is way too slow.

Time and Space Several types of improved adders have been designed: Carry Lookahead Adders Carry Skip Adders Carry Select Adders Adder Type Time Size 32 bit adder, 7ns ripple ------------------------------------------------------------------------------------- Ripple O(n) O(n) 7 * 32 = 224 Carry Lookahead O(log n) O(n log n) 7 * log 32 = 35 Carry Skip O(sqrt(n)) O(n) 7 * sqrt 32 = 40 Carry Select O(sqrt(n)) O(n) 7 * sqrt 32 = 40

Time and Space Notice that the Carry Lookahead Adder is the fastest, but also the largest! The Carry Lookahead Adder generates the carry signals by generating the P and G signals described in the text. This added circuitry is responsible for the large size of this adder. The Carry Skip Adder only generates the P signals The Carry Select Adder uses two complete adders, one with a carry in of 1 and the other 0.

Fast Multipliers Many adders can be used in parallel to speed multiplication. These units are called parallel multipliers. The important issue is that increased speed can be achieved by throwing hardware at the problem. Parallel multipliers can be pipelined to allow a multiplication to begin on each clock cycle. The result still takes N clock cycles, but then a new result becomes available each clock cycle after the first.

Conclusions Algorithms such as binary addition for integer or floating point can usually be made faster by throwing more hardware at the problem. It is the job of the architect and the implementor to make the speed versus cost trade-offs. Understanding the way the datapath of a machine is implemented is crucial for compiler and operating system writers.