Wireless Sensor Network A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution* by Banit Agrawal *Paper published in CASES 2005 by U Michigan Group 9/18/2018 Banit Agrawal @ UCSB

Outline Introduction Applications of wireless sensor networks Wireless Sensor Network (WSN) Architecture WSN’s Microprocessor UMich first generation processor UMich second generation processor Conclusion 9/18/2018 Banit Agrawal @ UCSB

What is wireless sensor network Wireless Sensor Network (WSN) Network of many small distributed computers for processing the sensor data Usually consists of microprocessor, memory, transceiver, sensing device, battery/energy scavenging unit, etc Resource constrained Everything optimized for low-energy operations 9/18/2018 Banit Agrawal @ UCSB

Current Challenges Energy Conservation Limited Computation/Storage Scalability Fault-tolerance Routing/Communication Bandwidth Autonomous and Distributed Systems Security 9/18/2018 Banit Agrawal @ UCSB

Applications (1) Health monitoring Environmental Monitoring Habitat Monitoring Integrated Biology Structural Monitoring Building/Border/Battlefield detection Road/traffic monitoring Health monitoring 9/18/2018 Banit Agrawal @ UCSB

Applications (2) Context-aware computing Automation Business Applications Supply Chain Management Expired/Damaged Goods Tracking Automatic Checkout Systems Security, surveillance Context-aware computing Automation 9/18/2018 Banit Agrawal @ UCSB

WSN Node Architecture Ref: Energy-Aware Wireless Microsensor Networks 9/18/2018 Banit Agrawal @ UCSB

Berkeley Motes 9/18/2018 Banit Agrawal @ UCSB

Sensoria SGATE hardware Processor RAM Flash GPS Address/Data Bus DSP Preprocessor Multi- Channel Sensor Interface Analog Front End Imager Module Modular Wireless and Digital Interfaces RF Modem 1 2 Digital I/O 10/100 Ethernet 9/18/2018 Banit Agrawal @ UCSB

UCLA Sensor Nodes 9/18/2018 Banit Agrawal @ UCSB

MIT AMPS 9/18/2018 Banit Agrawal @ UCSB

Intel StarGate 9/18/2018 Banit Agrawal @ UCSB

Harvard’s University (ISCA’05) Micro Controller Event Processor System Bus Interrupt Power Ctrl Addr/Data SRAM Sensors Radio Message Processor Data Filter Timer 9/18/2018 Banit Agrawal @ UCSB

Berkeley’s Experimental Platform Telos 4/04 Robust Low Power 250kbps Easy to use Services Networking TinyOS Small microcontroller 8 kB code 512 B data Simple, low-power radio 10 kbps ASK EEPROM (32 KB) Simple sensors WeC 99 “Smart Rock” Rene 11/00 Designed for experimentation sensor boards power boards Mica 1/02 NEST open exp. Platform 128 kB code, 4 kB data 40kbps OOK/ASK radio 512 kB Flash Dot 9/01 Demonstrate scale Mica2 12/02 38.4kbps radio FSK Spec 6/03 “Mote on a chip” Ref: HotChips 2004 – “Mote Evolution…” 9/18/2018 Banit Agrawal @ UCSB

Mote Evolution Ref: HotChips 2004 – “Mote Evolution…” 9/18/2018 Banit Agrawal @ UCSB

WSN’s Microcontroller AT/ATmega/ATMEL (AVR) Family TI Family Intel XScale StrongARM Harvard’s microcontroller UMich’s first generation processor UMich’s second generation processor 9/18/2018 Banit Agrawal @ UCSB

Processor Requirements 9/18/2018 Banit Agrawal @ UCSB

Not Performance, Energy is important. Voltage Reduction Not Performance, Energy is important. 9/18/2018 Banit Agrawal @ UCSB

Sensor Network Applications Representative set to evaluate architecture 9/18/2018 Banit Agrawal @ UCSB

Optimizing Energy Efficiency Reduce the area to minimize the static power Transistor utility must be maximized CPI must be minimized 9/18/2018 Banit Agrawal @ UCSB

Processor’s Characteristics 12-bit RISC ISA 8-bit datapaths Flexible Operand Handling Application specific instructions Prefetch mechanism Memory Architecture Branch speculation and out-of-order execution 9/18/2018 Banit Agrawal @ UCSB

ISA: RISC Encoding 12-bit RISC encoding simple decoding logic Reducing code-density and hence area to reduce the leakage energy 96.2% encoding efficiency 9/18/2018 Banit Agrawal @ UCSB

ISA Organization 9/18/2018 Banit Agrawal @ UCSB

ISA Design Load-store architecture Simple to design and pipeline 8 registers Simple to design and pipeline 2-operand based design Preserve bit to save the source Various addressing modes available 9/18/2018 Banit Agrawal @ UCSB

ISA Design (2) Micro-operations Application specific instructions Efficient pointer and carry manipulation Event scheduler control Timer control Reduction in code-size 9/18/2018 Banit Agrawal @ UCSB

Data memory predecode architecture [May not be useful for pointers] Memory Optimizations Data memory predecode architecture [May not be useful for pointers] 9/18/2018 Banit Agrawal @ UCSB

Memory Optimizations (2) Instruction memory predecode architecture 2 words and automatically increment the page when PC reaches the end of page 9/18/2018 Banit Agrawal @ UCSB

Processor pipeline design 3-stage pipeline [optimum, not 4 not 2] 9/18/2018 Banit Agrawal @ UCSB

Microarchitectural Optimizations Out-of-order execution Taken branch speculation 9/18/2018 Banit Agrawal @ UCSB

Results 9/18/2018 Banit Agrawal @ UCSB

Results: Contributions Storage unit and other components 9/18/2018 Banit Agrawal @ UCSB

Related Works 8-bit ATmega - 1.5 nJ/instruction Clever Dust 2 – 12 pJ/instruction StrongARM/XScale - 1nJ/instruction SNAP/LE – 24 pJ/instruction Umich first generation – 1.6 pJ/instruction Umich second generation – 600fJ/instruction 9/18/2018 Banit Agrawal @ UCSB

Conclusion Energy-efficient processor (600 fJ/instruction, will run 312 years on single AAA) Microarchitectural and ISA optimizations to reduce the leakage energy IBM 130nm fabrication Intra-ocular pressure sensor 9/18/2018 Banit Agrawal @ UCSB

Thanks for your attention. Questions ? 9/18/2018 Banit Agrawal @ UCSB