Alan Mishchenko Department of EECS UC Berkeley ABC Overview This 10 minute presentation gives an overview of ABC: its history, place in the design flow, where it is used today, and future plans Alan Mishchenko Department of EECS UC Berkeley

Introduction ABC is a open-source logic synthesis and formal verification system developed by the group of Professor Robert Brayton at UC Berkeley Distributed under a BSD-like license ABC is a configurable and extensible toolbox containing efficient implementation of many relevant computations It has become standard in industry and academia for Performing tasks in logic synthesis and verification Learning state-of-the-art implementations Prototyping and benchmarking new solutions

History Started in 2005 as a “summer project” Unexpectedly took off with some industrial users switching to it from SIS as early as fall 2005 Many researchers and companies adopted ABC later Implementations continue to improve, some of them currently in the 4th generation 3

Place of ABC in Design Flow System specification Verification High-level synthesis ABC Logic synthesis Technology mapping Physical synthesis Manufacturing

ABC and IDEA Project At present, ABC is more of a toolbox than a full push-button solution It implements most of the synthesis, mapping, and verification computations needed in the design flow, but it lacks some for example, mapping of sequential logic into library flip-flops is missing However, ABC+Yosys is a full solution from RTL to a mapped netlist Assuming that “file.v” contains RTL Verilog and “file.lib” contains a Liberty Library, the following Yosys script is a “full solution” read_verilog file.v # RTL elaboration read_liberty -lib file.lib # Liberty file parsing synth # high-level synthesis dfflibmap -liberty file.lib # sequential logic mapping abc -liberty file.lib # synthesis and mapping by ABC opt_clean # post-processing write_verilog file_out.v # producing mapped netlist (script courtesy of Clifford Wolf, the developer of Yosys)

Where ABC Is Used It is impossible to say exactly how many companies use ABC and in what role It is safe to say that all major and many relevant minor companies evaluated ABC It is safe to say that ABC is industrial-strength used in industrial tools to replace obsolete methods and implementations used in many academic projects won 7 hardware model checking competitions conducted since 2007 (http://fmv.jku.at/hwmcc15/) received other performance awards for example, 2016 ICCAD CAD competition, Problem A

What’s Next A small plan A bigger plan The biggest plan Continue improving baseline implementations and experiment with new ideas on an ongoing basis A bigger plan Additionally, expand in the direction of the design entry Improve HDL interface Enable some form of high-level synthesis Develop strong word-level optimization and verification The biggest plan Additionally, rewrite the codebase to make ABC more efficient, flexible, and useful for a wider range of tasks

Summary Introduced ABC Reviewed its history Outlined its place in the design flow Discussed where and how it is used Suggested next steps in the development