Samuel Luckenbill1, Ju-Yueh Lee2, Yu Hu3, Rupak Majumdar1, and Lei He2

Slides:



Advertisements
Similar presentations
ENGIN112 L7: More Logic Functions September 17, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 7 More Logic Functions: NAND, NOR,
Advertisements

A. Darwiche Knowledge Compilation Jinbo Huang NICTA and ANU Slides made by Adnan Darwiche and Jinbo Huang.
Address comments to FPGA Area Reduction by Multi-Output Sequential Resynthesis Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1.
Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Delta Debugging and Model Checkers for fault localization
Queries with Difference on Probabilistic Databases Sanjeev Khanna Sudeepa Roy Val Tannen University of Pennsylvania 1.
Copyright 2004 Koren & Krishna ECE655/DataRepl.1 Fall 2006 UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Fault Tolerant Computing.
Every Bit Counts – Fast and Scalable RFID Estimation Muhammad Shahzad and Alex X. Liu Dept. of Computer Science and Engineering Michigan State University.
NATW 2008 Using Implications for Online Error Detection Nuno Alves, Jennifer Dworak, R. Iris Bahar Division of Engineering Brown University Providence,
Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage Tao Li Zhiping Yu Institute of Microelectronics Tsinghua University.
ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions.
February 23, 2015CS21 Lecture 201 CS21 Decidability and Tractability Lecture 20 February 23, 2015.
4/27/2006 ELEC7250: White 1 ELEC7250 VLSI Testing: Final Project Andrew White.
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
ELEC 7250 Term Project Presentation Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL.
Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1 Electrical.
Address comments to Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching Yu Hu 1, Zhe Feng 1, Lei He 1 and Rupak Majumdar 2.
Jan 6-10th, 2007VLSI Design A Reduced Complexity Algorithm for Minimizing N-Detect Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.
 Y. Hu, V. Shih, R. Majumdar and L. He, “Exploiting Symmetries to Speedup SAT-based Boolean Matching for Logic Synthesis of FPGAs”, TCAD  Y. Hu,
A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs Kanupriya Gulati Nikhil Jayakumar Sunil P. Khatri Department of.
. PGM 2002/3 – Tirgul6 Approximate Inference: Sampling.
Worst-Case Timing Jitter and Amplitude Noise in Differential Signaling Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, and Yu Hu Electrical Engineering Dept.,
Time Series Data Analysis - II
USING SAT-BASED CRAIG INTERPOLATION TO ENLARGE CLOCK GATING FUNCTIONS Ting-Hao Lin, Chung-Yang (Ric) Huang Graduate Institute of Electrical Engineering,
Exercise problems for students taking the Programming Parallel Computers course. Janusz Kowalik Piotr Arlukowicz Tadeusz Puzniakowski Informatics Institute.
Digitaalsüsteemide verifitseerimise kursus1 Formal verification: BDD BDDs applied in equivalence checking.
Binary Decision Diagrams (BDDs)
Binomial Distributions Calculating the Probability of Success.
Probabilistic Mechanism Analysis. Outline Uncertainty in mechanisms Why consider uncertainty Basics of uncertainty Probabilistic mechanism analysis Examples.
MBSat Satisfiability Program and Heuristics Brief Overview VLSI Testing B Marc Boulé April 2001 McGill University Electrical and Computer Engineering.
FAULT TREE ANALYSIS (FTA). QUANTITATIVE RISK ANALYSIS Some of the commonly used quantitative risk assessment methods are; 1.Fault tree analysis (FTA)
Week 10Complexity of Algorithms1 Hard Computational Problems Some computational problems are hard Despite a numerous attempts we do not know any efficient.
Inference Complexity As Learning Bias Daniel Lowd Dept. of Computer and Information Science University of Oregon Joint work with Pedro Domingos.
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
On the Relation between SAT and BDDs for Equivalence Checking Sherief Reda Rolf Drechsler Alex Orailoglu Computer Science & Engineering Dept. University.
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
Technology Mapping. 2 Technology mapping is the phase of logic synthesis when gates are selected from a technology library to implement the circuit. Technology.
Bayesian networks and their application in circuit reliability estimation Erin Taylor.
Output Grouping Method Based on a Similarity of Boolean Functions Petr Fišer, Pavel Kubalík, Hana Kubátová Czech Technical University in Prague Department.
In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He Electrical Engineering Dept., UCLA Presented by Ju-Yueh Lee Address comments.
MAT 4830 Mathematical Modeling 04 Monte Carlo Integrations
IPR: In-Place Reconfiguration for FPGA Fault Tolerance Zhe Feng 1, Yu Hu 1, Lei He 1 and Rupak Majumdar 2 1 Electrical Engineering Department 2 Computer.
Fault-Tolerant Resynthesis for Dual-Output LUTs Roy Lee 1, Yu Hu 1, Rupak Majumdar 2, Lei He 1 and Minming Li 3 1 Electrical Engineering Dept., UCLA 2.
NP-Completeness (2) NP-Completeness Graphs 4/13/2018 5:22 AM x x x x x
Random Numbers and Simulation
Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching
A New Algorithm for Computing Upper Bounds for Functional EmajSAT
NP-Completeness (2) NP-Completeness Graphs 7/23/ :02 PM x x x x
NP-Completeness (2) NP-Completeness Graphs 7/23/ :02 PM x x x x
NP-Completeness Proofs
Hard Problems Introduction to NP
Delay Optimization using SOP Balancing
VLSI Testing Lecture 7: Combinational ATPG
Possibilities and Limitations in Computation
Queries with Difference on Probabilistic Databases
LPSAT: A Unified Approach to RTL Satisfiability
Overview: Fault Diagnosis
NP-Completeness (2) NP-Completeness Graphs 11/23/2018 2:12 PM x x x x
SAT-Based Area Recovery in Technology Mapping
Yiyu Shi*, Wei Yao*, Jinjun Xiong+ and Lei He*
VLSI Testing Lecture 7: Combinational ATPG
Alan Mishchenko UC Berkeley (With many thanks to Donald Knuth,
المشرف د.يــــاســـــــــر فـــــــؤاد By: ahmed badrealldeen
Alan Mishchenko UC Berkeley (With many thanks to Donald Knuth for
Delay Optimization using SOP Balancing
Canonical Computation without Canonical Data Structure
NP-Completeness (2) NP-Completeness Graphs 7/9/2019 6:12 AM x x x x x
Alan Mishchenko Department of EECS UC Berkeley
Presentation transcript:

RALF: Reliability Analysis for Logic Faults – An Exact Algorithm and its Applications Samuel Luckenbill1, Ju-Yueh Lee2, Yu Hu3, Rupak Majumdar1, and Lei He2 1Computer Science Dept., UCLA 2Electrical Engineering Dept., UCLA 3Electrical Engineering Dept., University of Alberta, Edmonton Canada

Outline RALF Overview Circuit Representation Algorithms Experimental results

RALF Features Single-gate criticality: The probability that a flipped bit at one gate will affect the output Full-chip fault rate: The average criticality over all gates in a circuit

Applications for RALF Circuit optimization for reliability Random pattern-resistant fault identification to enhance testability Optimality studies of approximate algorithms

RALF System Exact symbolic algorithm Compiles miter to d-DNNF (similar to BDD) Computes criticality in one pass over d-DNNF Circuit Miter CNF d-DNNF Fault Rate

Miter-Based Calculation Criticality of G: Fraction of assignments to primary inputs Xi for which O = 1

Compiled Circuit Representation Deterministic Decomposable Negation Normal Form (d-DNNF) A subset of NNF which satisfies Decomposability Determinism

Why d-DNNF? Almost as powerful as BDD Polytime operations include SAT, model counting, and model enumeration Usually more concise than BDD and faster to compile Determinism and decomposability make the criticality computation efficient Compiler: http://reasoning.cs.ucla.edu/c2d

Negation Normal Form A B  B A C  D D  C and or A circuit representation where all of the inverters have been pushed to the inputs and all internal nodes are either AND or OR.

Decomposability or and and or or or or and and and and and and and and No two children of AND share a variable or and and A,B C,D or or or or Decomposability only applies to AND nodes. An AND node is decomp. If its children do not mention the same variable. An NNF is decomposable if every AND node in the graph is decomposable. and and and and and and and and A B  B A C  D D  C

Determinism or and and or or or or and and and and and and and and A No two children of OR share a satisfying assignment or and and or or or or Determinism on the other hand is a property of OR nodes. An OR node is deterministic if its children do not share a model and we say that an NNF is deterministic if every OR node in the graph is deterministic. and and and and and and and and A B  B A C  D D  C

Criticality Algorithm d-DNNF is a representation of the miter Invariant: at each node, we compute the probability that the circuit below it evaluates to 1 Value computed at root is the criticality of the faulty node in the miter Computation is linear in d-DNNF size

Evaluating d-DNNF α α β β Pr(L) 1 - Pr(L) (e.g. 0.5 for a uniform distribution over the inputs) L 1 - Pr(L) L The value of a leaf node is simply the probability that the primary input it represents is set to true The value of an AND node is the product of its children’s values The value of an OR node is the sum of its children’s values AND Pr(AND) = Pr(α) * Pr(β)(Requires Decomposability) α β OR Pr(OR) = Pr(α) + Pr(β) (Requires Determinism) α β

Circuit Characteristics Tractability Circuit Characteristics Performance Name Gates Inputs d-DNNF Nodes BDD Nodes Compile Time Total Run Time i7 581 199 79637 - 138.24 mult32a 535 34 166976 118.85 i6 455 138 67295 895599 58.31 i5 402 133 507965 59.99 b9 296 41 725729 67.97 i4 292 192 20231 3.78 my_adder 259 33 29865 116621 10.03 cht 244 47 175055 2084948 8.55 i2 238 201 103434 398017 4.84 lal 234 26 523283 67.77

Random-Pattern Resistant Faults Logic Masking

Detection of Random-Pattern Resistant Faults

Fidelity of Monte Carlo Simulation

Conclusion RALF performs surprisingly well on MCNC circuits, despite being an exact algorithm RALF uses d-DNNF, a less powerful but usually more succinct circuit representation than BDD. For criticality and fault-rate computation, Monte Carlo simulation is good enough for most circuits

Thank you