Analog to Digital Converters Nyquist-Rate ADCs Flash ADCs Sub-Ranging ADCs Folding ADCs Pipelined ADCs Successive Approximation (Algorithmic) ADCs Integrating (serial) ADCs Oversampling ADCs Delta-Sigma based ADCs Fischer 08

Conversion Principles Fischer 08

ADC Architectures Flash ADCs: High speed, but large area and high power dissipation. Suitable for low-medium resolution (6-10 bit). Sub-Ranging ADCs: Require exponentially fewer comparators than Flash ADCs. Hence, they consume less silicon area and less power. Pipelined ADCs: Medium-high resolution with good speed. The trade-offs are latency and power. Successive Approximation ADCs: Moderate speed with medium-high resolution (8-14 bit). Compact implementation. Integrating ADCs or Ramp ADCs: Low speed but high resolution. Simple circuitry. Delta-Sigma based ADCs: Moderate bandwidth due to oversampling, but very high resolution thanks to oversampling and noise shaping. Fischer 08

Performance Limitations 1 n-Bit ADC Sinusoidal Input Swing: ±1[V] fmax= ½ fconv System Definitions Thermal Noise Limitation Clock Jitter (Aperture) Limitation Normalized Noise Powers: fin=½fconv Limiting Condition: Maximum Resolution: Fischer 08

Performance Limitations 2 Displays Seismology Audio Sonar Wireless Communications Ultra Sound Video  Selection of ADC Architecture is driven by Application Fischer 08

Parallel or Flash ADCs Conceptual Circuit Fischer 08

Sub-Ranging ADCs Half-Flash or Two-Step ADC Fischer 08

Folding ADCs Principle Configuration … 2n1 Sub-Ranges Fischer 08

Folding Processor Example: 2-Bit Folding Circuit Fischer 08 (2n-1+1)Io for n-Bit 2Io Fischer 08

Successive Approx. ADCs Implementation Concept Fischer 08

DAC Realization 1 (Voltage Mode) Fischer 08

DAC Realization 2 Spread Reduction through R-2R Ladder Fischer 08

DAC Realization 3 Charge-Redistribution Circuit Pros valid only during f2 Pros Insensitive w.r.t. Op-amp Gain Offset (1/f Noise) compensated Cons Requires non-overlapping Clock High Element Spread  Area Output requires S&H Fischer 08

DAC Realization 4 Spread Reduction through capacitive Voltage Division Example: 8-Bit ADC valid only during f2 Spread=2n/2 Fischer 08

DAC Realization 5 Charge-Redistribution Circuit with Unity-Gain Amplifier Example: 8-Bit ADC Amplifier Input Cap. 16/15C Spread=½2n/2 Cp  Gain Error: єG=-Cp/16C Pros Voltage divider reduces spread Buffer  low output impedance No clock required Cons Parasitic cap causes gain error High Op-amp common mode input required No amplifier offset compensation Fischer 08

DAC8 with Unity-Gain Amplifier Sub-range Output (4 LSBs) 0.5u 2u 1.5u 2.5u 3.5u 4.5u 5.5u 6.5u 3u 4u 5u 6u 1u Amplifier Output 6.5u 0.5u 2u 1.5u 2.5u 3.5u 4.5u 5.5u 3u 4u 5u 6u 1u Fischer 08

DAC Realization 6 Current Mode Implementation Fischer 08

Current Cell & Floor Plan Symmetrical Current Cell Placement Array of 256 Cells Unit Current Cell R Iout Current summing Rail Switching Devices Cascode Current Source Fischer 08

DAC Implementation Layout of 10-Bit Current-Mode DAC (0.5mm CMOS) Current summing Rails Fischer 08

Modified SA Algorithm 1 Idea: Replace DAC by an Accumulator  Consecutively divide Ref by 2 Fischer 08

Modified SA Algorithm 2 Idea: Maintain Comparator Reference (½ FS=Gnd)  Double previous Accumulator Output First cycle only Accumulator Fischer 08

SC Implementation SC Implementation of modified SA ADC Fischer 08

Timing Diagram Fischer 08

Offset Compensated Circuit Offset Compensated SC Implementation Fischer 08

Building Blocks 1 Transconductance Amplifier DC Gain 77 dB Gain-bandwidth 104 MHz @ CL= 1.5 pF Power 1.3 mW Output Swing 4 V p-p Fischer 08

Building Blocks 2 Latched CMOS Comparator Power 0.5 mW Resolution > 0.5 mV Settling Time 3 ns Fischer 08

Layout of 8-Bit ADC 165 mm (0.5 mm CMOS) Fischer 08

Spice Simulation (Bsim3) 8-Bit ADC: fclk=10MHz  fconv=1.25MHz Fischer 08

Pipelined ADCs Pipelined modified SA or Algorithmic ADC Pros Offset (1/f Noise) compensated Minimum C-spread One conversion every clock period Cons Matching errors  digital correction for n>8 Clock feed-through very critical High amplifier slew rate required Fischer 08

Integrating or Serial ADCs Dual Slope ADC Concept Constant Ramp Prop. to Input Ramp Using 2N/k samples requires Ref = FS/k reduced Integrator Constant (Element Spread) N represents digital equivalent of analog Input Fischer 08

SC Dual-Slope ADC 10-Bit Dual-Slope ADC Fischer 08

ADC Testing Types of Tests Static Testing Dynamic Testing In static testing, the input varies slowly to reveal the actual code transitions.  Yields INL, DNL, Gain and Offset Error. Dynamic testing shows the response of the circuit to rapidly changing signals. This reveals settling errors and other dynamic effects such as inter-modulation products, clock-feed-trough, etc. Circuit Under Test Output Input Clock Fischer 08

Performance Metrics 1 Static Errors Error Types Offset Gain INL DNL IDEAL ADC Error Types Offset Gain DNL INL Missing Codes Fischer 08

Performance Metrics 2 Frequency Domain Characterization Amplitude fsig Amplitude Ideal n-Bit ADC: SNR = 6.02 x n + 1.76 [dB] Fischer 08

ADC Error Sources Static Errors Dynamic Errors Element or Ratio Mismatches Finite Op-amp Gain Op-amp & Comparator Offsets Deviations of Reference Dynamic Errors Finite (Amplifier) Bandwidth Op-amp & Comparator Slew Rate Clock Feed-through Noise (Resistors, Op-amps, switched Capacitors) Intermodulation Products (Signal and Clock) Fischer 08

Static Testing Servo-loop Technique Comparator, integrator, and ADC under test are in negative feedback loop to determine the analog signal level required for every digital code transition. Integrator output represents equivalent analog value of digital output. Transition values are used to generate input/output characteristic of ADC, which reveals static errors like Offset, Gain, DNL and INL. Fischer 08

Dynamic Testing Test Set-up Types of Dynamic Tests Histogram or Code-Density Test FFT Test Sine Fitting Test Fischer 08

Histogram or Code-Density Test DNL appears as deviation of bin height from ideal value. Integral nonlinearity (INL) is cumulative sum (integral) of DNL. Offset is manifested by a horizontal shift of curve. Gain error shows as horizontal compression or decompression of curve. Fischer 08

Histogram Test Pros and Cons of Histogram Test Histogram test provides information on each code transition. DNL errors may be concealed due to random noise in circuit. Input frequency must be selected carefully to avoid missing codes (fclk/fin must be non-integer ratio). Input Swing is critical (cover full range) Requires a large number of conversions (o 2n x 1,000). Fischer 08

Simulated Histogram Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset Fischer 08

FFT Test Pros and Cons of FFT Test Offers quantitative Information on output Noise, Signal-to-Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR) and Harmonic Distortion (SNDR). FFT test requires fewer conversions than histogram test. Complete characterization requires multiple tests with various input frequencies. Does not reveal actual code conversions Fischer 08

Simulated FFT Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset SNDR=49 dB  ENOB=7.85 SFDR=60 dB Fischer 08