Stratix 10 External Memory Interface Board Guidelines Quartus Prime Software v17.0ir3 Stratix 10 EMIF Board Guidelines are preliminary and subject to change

Introduction This slide deck covers the following topics: Layout recommendations Signal matching/skew For more details regarding board design, refer to the appropriate Board Design Guidelines section in the External Memory Interface Handbook DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines LPDDR2 and LPDDR3 SDRAM Board Design Guidelines RLDRAM II and RLDRAM3 Board Design Guidelines QDR II and QDR-IV SRAM Board Design Guidelines *EMIF = External Memory Interface

Software Requirements Quartus Prime Software v17.0ir3

Disclaimer This slide deck covers layout guidance for DDR3 and DDR4 This document only covers key board layout requirements Please check with your DRAM vendor for any additional layout guidance Length matching guidelines are recommendations Should not be considered as hard guidelines Board-level simulation must be performed to ensure there are no signal integrity or ISI/Crosstalk related issues To ensure there are no timing violations Enter accurate information in the Board tab of the EMIF IP GUI For more details on simulation guidance refer to this wiki page

Reference Stack-Up Starting Est. Thick. DK/DF L Y R # Single-Ended Model Differential Model Dielectric Org. L/W A/W L/W Fin. L/W Ref. Plane Calc. Imp. Org. space A/W space Fin. space 1 S 3/8 oz + Platting 3/8 2.45 6 7.2 2 50 4 100 2x1025 (70% rc) => 4.05 3.35/.002 P 2.60 1035 Core 2.00 3.46/.002 3 2x1035 (70% rc) 3.60 H 0.65 4.8 3,6 3.3 8.2 4.5 7 3313 Core 4.00 3.71/.002 5 3.5 3.4 3.25 8.25 1035HR (75% rc) 3.28/.002 1.30 8 7,10 3.2 8.3 9 10 11 1078 (72% rc) 3.20 3.31/.002 12 3.6 11,13 7.9 13 14 13,16 15 16 17 16,18 18 This is the stack-up used to simulate Stratix 10 memory interfaces

General Board Guidelines The following slides cover board guidelines for DDR3 and DDR4 protocols Trace impedance plays an important role in signal integrity Based on the stack-up (mentioned on the previous slide), these impedances are recommended: 45Ω for single-ended traces 90Ω for differential traces To minimize PCB layer propagation variance, it is recommended to route signals from the same net group on the same layer Use 45° angles (not 90° corners) Disallow critical signals across split planes Route over appropriate VCC and GND planes Keep signal routing layers close to GND and power planes

Layout Recommendation Summary DDR3 DDR4 Max Length (Discrete Devices) 7 inches for Addr/Cmd 5 inches for DQS/DQ/DM Max Length (DIMM) 4.5 inches Data Group Skew Match DQS/DQ/DM within 20ps Address/Command VS Clock Skew Match Addr/Cmd signals within 20ps of Mem CK Package Skew Matching Yes Data Strobe to Mem CK Matching Refer to slide 10 Clock Matching 2ps within a clock pair 5ps between clock pairs Spacing Guideline (Data/Data Strobe/Addr/Cmd) 3H spacing between any Data, Data Strobe, and Addr/Cmd traces1 Spacing Guideline (Mem CK) 5H spacing between Mem CK and any other signal1 1 Where H is the distance to the nearest return path

Data to Data Strobe Delay Matching Match the (package + board) trace delays up to 20ps of skew for signals within a data group Data, Data strobe, Data mask For more information on how to perform package de skew, refer to the Package Deskew section in the External Memory Interface Handbook Package Trace Length Board Trace Length DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS DQS_N Inside FPGA On PCB

Data Bus Matching Requirement Stratix 10 devices can support DDR4 frequencies up to 1333MHz To ensure robustness for DDR4 interfaces at 1333MHz, the following requirement must be met: Trace delays (package + PCB) for all DQS/DQS#, DQ, DBI/DM signals must be matched within 50ps This requirement is required for DDR4 DIMM interfaces running at 1333MHz This requirement is strongly recommended for any DDR3/DDR4 configuration running at 1066MHz or above For more information on how to perform package de skew, refer to the Package Deskew section in the External Memory Interface Handbook

Address/Command/Control Skew The following slides go into detail explaining board guidelines in reference to Address/Command/Control signals All Addr/Cmd/Control signals should match up to ±20ps compared to the Mem CK trace For example: If Mem CK trace delay is 500ps Allowed range for Addr/Cmd/Control signals is 480ps to 520ps For discrete components: Make sure ±20ps recommendation is met for each component in fly-by chain For DIMMs: Make sure the ±20ps recommendation is met at each DIMM connector Applicable to single and multiple DIMM configurations

Address/Command/Control Skew x(n) represents the clock trace length between FPGA and DRAM components, where n = 1, 2, 3… y(n) represents Addr/Cmd trace length between FPGA and DRAM components, where n = 1, 2, 3… Route all Addr/Cmd signals to match clock signals within ±20ps or approximately ±3.175mm to each discrete memory component x = y ± 20ps x + x1 = y + y1 ± 20ps x + x1 + x2 = y + y1 + y2 ± 20ps x + x1 + x2 + x3 = y + y1 + y2 + y3 ± 20ps FPGA DDR3 SDRAM Component VTT x3 y3 y2 y1 y x2 x1 x Clock Addr/Cmd Propagation Delay < 0.69 tCK

Data Strobe to Mem CK Matching Timing between data strobe and clock signals on each device calibrate dynamically to meet tDQSS To make sure skew is not too large for leveling circuit’s capability: Propagation delay of clock signal must not be shorter than propagation delay of DQS signal at every device CKi – DQSi > 0 0 < i < number of components – 1 Total skew of CLK and DQS signal between groups is less than one clock cycle Max(CKi + DQSi) – min(CKi + DQSi) < 1 × tCK For DIMM topology: Delay and skew must take into consideration values of actual DIMM DDR3 Component VTT FPGA … DQ Group 0 DQ Group 1 DQ Group i CK DQS CK0 CK1 CKi Cki = Clock signal propagation delay to device i DQSi = DQ/DQS signals propagation delay to group i

Spacing Guidelines Avoid routing two signal layers next to each other Always make sure signals related to memory interfaces are routed between appropriate GND or power layers DQ/DQS/DM traces: Maintain at least 3H spacing between edges (air-gap) of traces Address/Command/Control traces: Mem Clock traces: Maintain at least 5H spacing between two clock pairs or a clock pair and any other memory interface trace GND or Power 3H H 5H PCB cross-section H is the vertical distance to the closest return path for a particular trace