Chapter 11 Multiple interrupts

Slides:



Advertisements
Similar presentations
Lab III Real-Time Embedded Operating System for a SoC System.
Advertisements

Exceptions. Exception Types Exception Handling Vectoring Interrupts Interrupt Handlers Interrupt Priorities Interrupt applications 6-2.
Interrupts, Low Power Modes and Timer A (Chapters 6 & 8)
Chung-Ta King National Tsing Hua University
A look at interrupts What are interrupts and why are they needed.
68HC11 Polling and Interrupts
Chapter 10 Timer and external hardware interrupts CEG Microcomputer Systems chapter 10: Timer and external interrupts v4b 1
ECE 372 – Microcontroller Design Parallel IO Ports - Interrupts
Chapter 11 Multiple interrupts CEG Microcomputer Systems CEG2400 Ch11 Multiple Interrupts V4c
Chapter 12: Software interrupts (SWI) and exceptions
COMP3221: Microprocessors and Embedded Systems Lecture 15: Interrupts I Lecturer: Hui Wu Session 1, 2005.
A look at interrupts What are interrupts and why are they needed in an embedded system? Equally as important – how are these ideas handled on the Blackfin.
Communication Lab - Interrupts 1/13 Sequential Programming  Our C++ programs are sequential ( סדרתיים), they start at the first instruction and end at.
A look at interrupts What are interrupts and why are they needed.
Chapter 6 Interrupts (I. Scott Mackenzie).
Chapter 9: Hardware Interrupts -- IRQ=External Interrupt Request
The 8051 Microcontroller and Embedded Systems
INTERRUPTS PROGRAMMING
Lecture 9 Timer Operations and Programming. 2  Introduction  Summary of timers  Timer programming sequence  Summary of timer SFRs  Timer 0: 8-bit.
ECE 265 – LECTURE 12 The Hardware Interface 8/22/ ECE265.
COMP201 Computer Systems Exceptions and Interrupts.
UNIT 8 Keypad Interface Contact Closure Counter Exceptions (Interrupts and Reset)
Ch. 9 Interrupt Programming and Real-Time Sysstems From Valvano’s Introduction to Embedded Systems.
Microprocessors 1 MCS-51 Interrupts.
1 ARM University Program Copyright © ARM Ltd 2013 Using Direct Memory Access to Improve Performance.
1 Interrupts, Resets Today: First Hour: Interrupts –Section 5.2 of Huang’s Textbook –In-class Activity #1 Second Hour: More Interrupts Section 5.2 of Huang’s.
AT91 Interrupt Handling. 2 Stops the execution of main software Redirects the program flow, based on an event, to execute a different software subroutine.
ECE 447 Fall 2009 Lecture 7: MSP430 Polling and Interrupts.
Interrupts  An interrupt is any service request that causes the CPU to stop its current execution stream and to execute an instruction stream that services.
System Integration Module MTT Motoola SYSTEM INTEGRATION MODULE (SIM)
Chapter 5 - Interrupts.
Embedded Systems Design 1 Lecture Set 8 MCS-51 Interrupts.
EE/CS-352: Embedded Microcontroller Systems Part V The 8051 Assembly Language Interrupts.
Lecture 3 CSE 341 – Microprocessors Lecture 3 Md. Omar Faruqe UB 1228
CS-280 Dr. Mark L. Hornick 1 Sequential Execution Normally, CPU sequentially executes instructions in a program Subroutine calls are synchronous to the.
Interrupts ELEC 330 Digital Systems Engineering Dr. Ron Hayne
Interrupts ELEC 330 Digital Systems Engineering Dr. Ron Hayne Images Courtesy of Ramesh Gaonkar and Delmar Learning.
The 8051 Microcontroller Chapter 6 INTERRUPTS. 2/29 Interrupt is the occurrence of a condition an event that causes a temporary suspension of a program.
Introduction to Exceptions 1 Introduction to Exceptions ARM Advanced RISC Machines.
Chapter 10 Interrupts. Basic Concepts in Interrupts  An interrupt is a communication process set up in a microprocessor or microcontroller in which:
 The LPC2xxx devices currently have two on- chip UARTS.  Except UART1 has additional modem support.
A walk through interrupts on the PPC 823
Chapter 9: Hardware Interrupts -- IRQ=External Interrupt Request
Chapter 11 INTERRUPTS PROGRAMMING
Chapter 12: Software interrupts (SWI) and exceptions
Chapter 9: Hardware Interrupts -- IRQ=External Interrupt Request
Chapter 10 Timer and external hardware interrupts
ECE 3430 – Intro to Microcomputer Systems
8085 Interrupts LAKSHMI.B.E..
CS501 Advanced Computer Architecture
68HC11 Interrupts & Resets.
Microprocessor Systems Design I
Mon. Oct 2 Announcements Quiz Postponed to Wednesday – still only on 2.a + 2.b Video lecture for 2.a posted Lab 6 experiment extension You must come to.
The process starts from the I/O device
Timer and Interrupts.
Computer Architecture
Interrupts In 8085 and 8086.
Interrupt Source: under
Interrupt and Exception Programming
* * * * * * * 8051 Interrupts Programming.
Interrupts Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device The process.
Interrupt Source: under
8259 Programmable Interrupt Controller
Chapter 12: Software interrupts (SWI) and exceptions
COMPUTER PERIPHERALS AND INTERFACES
Interrupts.
Interrupt Source: under
Computer System Overview
Wireless Embedded Systems
COMP3221: Microprocessors and Embedded Systems
Presentation transcript:

Chapter 11 Multiple interrupts CEG2400 - Microcomputer Systems http://www.nxp.com/acrobat_download/usermanuals/UM10120_1.pdf (software) CEG2400 Ch11 Multiple Interrupts V7a

Overview To demonstrate multiple interrupts timer_int_demo1.c Control the on/off of the green LED by a switch CEG2400 Ch11 Multiple Interrupts V7a

To demonstrate multiple interrupts timer_int_demo1.c Important parts main(), init_timer_Eint () //init timer __irq isr_Eint3() //external interrupt, blink green-led CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a In part B, we will show how to change the state of the Green LED by pressing SW1 -- after pressing the switch SW1, the LED will change state once ( from on-to-off, or from off-to-on) Arm board red led CEG2400 Ch11 Multiple Interrupts V7a green led switch

Our testing board CEG2400 Ch11 Multiple Interrupts V7a CEG2400 Ch7: Driving Parallel Loads V1a 5 CEG2400 Ch11 Multiple Interrupts V7a

For 3.3V driving LEDs from a 3.3V system CEG2400 Ch7: Driving Parallel Loads V1a 6 CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a Advanced topic Nested interrupt using timer_int_demo1.c Multiple interrupt occurrences Timer External (a switch) Further references http://www.nxp.com/acrobat_download/applicationnotes/AN10254_2.pdf http://www.nxp.com/acrobat_download/applicationnotes/AN10381_1.pdf CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a Vectored interrupt concept Highest priority Slot0: Source: timer MCU with the Interrupt module LPC2131 2nd highest priority Slot1: external interrupt3 Source: EINt3 3nd highest priority Slot2: Others etc.. Source :E,g, UART CEG2400 Ch11 Multiple Interrupts V7a

Multiple interrupt example Nested interrupts can occur Timer1 set Main() {PINSEL1 = 0x00000300;//pin65=Eint3 void init_timer_Eint() :Do something : :} //Timer0 interrupt __irq isr_Timer0() { : } Blinks red-LED timer0 //external interrupt __irq isr_Eint3() { : blinks green-LED } Eint3 (pin65) Occurs when Eint3 is pulled down CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a The theory for External interrupt3 (EINT3) ISR Interrupt service routine for /EINT3 is _irq isr_Eint3() Not only the timer can generate interrupts, an external signal through EINT3 can also initiate an interrupt. An falling edge at EINT3 will trigger the execution of ISR void __irq isr_Eint3() External signal /EINT3 (p0.20, pin65) When /ENT3 is pulled down __irq isr_Eint3() Will be executed LPC2213x CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a 2i) /* Setup timer 0*/ Important 3 lines for timer (priority is 0 highest priority) 144)/* Setup the Timer Counter 0 Interrupt */ 145)void init_timer_Eint (void) { 146) T0PR = 0; // set prescaler to 0 147) T0MR0 =1382400; // set interrupt rate 10Hz, (interval=100mS) 148) // Pclk/10Hz = (11059200 x 5/4)/ 10 149) T0MCR = 3; // Interrupt and Reset on MR0 150) T0TCR = 1; // Timer0 Enable 151) VICVectAddr0 = (unsigned long) isr_Timer0; // set interrupt vector in 0 152) VICVectCntl0 = 0x20 | 4; // use it for Timer 0 Interrupt 153) VICIntEnable=0x1<<4;” // Enable Timer0 Interrupt, or “VICIntEnable = 0x00000010;” 154) 155) EXTMODE=0x08; // set EINT3 as edge trigger 156) VICVectAddr1 = (unsigned long)isr_Eint3; // set interrupt vector in 1 157) VICVectCntl1 = 0x20 | 17; // use it for EINT3 Interrupt 158) VICIntEnable |= 0x1<<17; // Enable EINT3 interrupt,or “VICIntEnable |= 0x00020000; ” 159) EXTINT = 0x08; // Clear EINT3 flag 160) } CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a 2ii) /* Setup external interrupt EINT3*/ Important 3 lines for Eint3 (external interrupt3) (priority is 1 2nd highest priority) 144)/* Setup the Timer Counter 0 Interrupt */ 145)void init_timer_Eint (void) { 146) T0PR = 0; // set prescaler to 0 147) T0MR0 =1382400; // set interrupt rate 10Hz, (interval=100mS) 148) // Pclk/10Hz = (11059200 x 5/4)/ 10 149) T0MCR = 3; // Interrupt and Reset on MR0 150) T0TCR = 1; // Timer0 Enable 151) VICVectAddr0 = (unsigned long) isr_Timer0; // set interrupt vector in 0 152) VICVectCntl0 = 0x20 | 4; // use it for Timer 0 Interrupt 153) VICIntEnable=0x1<<4;” // Enable Timer0 Interrupt, or “VICIntEnable = 0x00000010;” 154) 155) EXTMODE=0x08; // set EINT3 as edge trigger 156) VICVectAddr1 = (unsigned long)isr_Eint3; // set interrupt vector in 1 157) VICVectCntl1 = 0x20 | 17; // use it for EINT3 Interrupt 158) VICIntEnable |= 0x1<<17; // Enable EINT3 interrupt,or “VICIntEnable |= 0x00020000; ” 159) EXTINT = 0x08; // Clear EINT3 flag 160) } CEG2400 Ch11 Multiple Interrupts V7a

setup external interrupt line 155 (Eint3 is edge triggered) 155) EXTMODE=0x08; // set EINT3 as edge trigger 156) VICVectAddr1 = (unsigned long)isr_Eint3; // set interrupt vector in 1 157 VICVectCntl1 = 0x20 | 17; // use it for EINT3 Interrupt 158) VICIntEnable |= 0x1<<7;// Enable EINT3 intrp.or “VICIntEnable |= 0x20000;” 159) EXTINT = 0x08; // CEG2400 Ch11 Multiple Interrupts V7a

setup external interrupt line 156 155) EXTMODE=0x08; // set EINT3 as edge trigger 156) VICVectAddr1 = (unsigned long)isr_Eint3; // set interrupt vector in 1 157 VICVectCntl1 = 0x20 | 17; // use it for EINT3 Interrupt 158) VICIntEnable |= 0x1<<17; // Enable EINT3 intp,or“VICIntEnable |= 0x20000; ” 159) EXTINT = 0x08; // Point to which interrupt service program will run when EINT1 is pulled low CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a line 157) VICVectCntl1 = 0x20 | 17; // use it for EINT3 Interrupt, because 0x20=>bit 5=1 , is the IRQslot_en ‘17’ is the source mask of external interrupt1 (EINT3),(see next slide) 0x020  bit5=1 Each bit represents an interrupt source CEG2400 Ch11 Multiple Interrupts V7a

Source mask (same as the table in the last slide) E.g. timer0=4 external interrupt=15 CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a Exercise 11.1 Student ID: ___________,Date:_____________ Name: __________________________________ What is the interrupt source mask for UART 1? Answer: ?_____________________ How do you setup the pirorty of different interrupts? Answer: ?____________________________ CEG2400 Ch11 Multiple Interrupts V7a

Exercise: 11.2 Examples of other interrupt sources If you want to use Eint3(source mask=17) VICVectCntl1 = 0x20 | 17 VicIntEnable=?: Answer: VICIntEnable |= 0x00020000 (why?) If you want to use Eint0(source mask=14) VICVectCntl1 = 0x20 | 14 VicIntEnable=? Answer:?_________________________ If you want to use Uart0(source mask=6) VICVectCntl1 = 0x20 | 6 VicIntEnable=? Answer:?____________________________ CEG2400 Ch11 Multiple Interrupts V7a

setup external interrupt3 (EINT3) line 158 Bit17 is set 158) VICIntEnable |= 0x1<<17; // Enable EINT3 intp,or“VICIntEnable |= 0x20000; ” 159) EXTINT = 0x08; // Enable external interrupt 3 (EINT3) CEG2400 Ch11 Multiple Interrupts V7a

setup external interrupt line 159 155) EXTMODE=0x08; // set EINT3 as edge trigger 156) VICVectAddr1 = (unsigned long)isr_Eint3; // set interrupt vector in 1 157 VICVectCntl1 = 0x20 | 17; // use it for EINT3 Interrupt 158) VICIntEnable |= 0x00020000; // Enable EINT3 interrupt 159) EXTINT = 0x08; // External Interrupt Flag register (EXTINT - address 0xE01F C140) bit CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a 4) External interrupt3 (EINT3) Green-led changes state every time you press the interrupt switch SW1 130) //external interrupt 131) void __irq isr_Eint3() //runs when key depressed. 132 { 133) exint++; 134) //turn on /off the Green LED 135) if((exint%2)==0) 136) IO0SET|=GREEN_LED; 137) else IO0CLR|=GREEN_LED; 138) 139) EXTINT = 0x08; // Clear EINT3 flag 140) VICVectAddr = 0; // Acknowledge Interrupt 141) } CEG2400 Ch11 Multiple Interrupts V7a

Programming Exercise: study the following programs GPIO.c is a polling software program and a switch (SW1) to change the state of the Green LED timer_int_demo1.c is a program uses hardware external interrupt3 (EINT3) and a switch (SW1) to change the state of the Green LED. Compare the difference between timer_int_demo1.c and GPIO.c in terms of technology and performance CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a Summary Learned how to initialize an ARM system Learned how to use timer interrupt timer_int_demo1.c can be used as a template for building interrupt driven programs. CEG2400 Ch11 Multiple Interrupts V7a

Appendix (ESTR2100 students should study this) CEG2400 Ch11 Multiple Interrupts V7a

CEG2400 Ch11 Multiple Interrupts V7a Interrupt details : chapter5 of [1] from http://www.nxp.com/acrobat_download/usermanuals/UM10120_1.pdf Example UART generates an interrupt request and has the highest priory 0xffff f030 VICVectAddr reg contans, starting address of ISR_UART() : 0x0000 0018 LDR pc, [pc,#-0xFF0] Machine code:0xE51F FFF0 Interrupt service routine ISR_UART (software to handle UART) starting address is at VICVectAddr address reg 0xFFFF F030 At 0x18,the instruction is LDR pc, [pc,#-0xFF0] which will redirect Arm to executed ISR_UART() when UART interrupt request is received VIC places the address there automatically VIC IRQ_vector=0x18 ARM7TDMI Processor IRQ Or function Other interrupt sources UART Serial interface End of transmission CEG2400 Ch11 Multiple Interrupts V7a Logic_or all requests

CEG2400 Ch11 Multiple Interrupts V7a IRQ execution vector After initialization, any IRQ on UART0, SPI0, UART1 or I2C will cause jump to IRQ vector (0x18) Could put LDR pc, [pc,#-0xFF0] instruction there This instruction loads PC with the address that is present in VICVectAddr (0xFFFFF030) register! (meaning goto the address in VICVectAddr=0xFFFF F030) LDR pc, [addr]  goes to PC+8+addr Since “-0x0000 0ff0”=0xFFFFF00F+1=0xFFFFF010 PC=0x18+8+-0x0ff0=0x20 +0xFFFFF010= 0xFFFFF030 so LDR pc, [pc,#-0xFF0] will branch to 0xFFFFF030 This instruction handles all 32 hardware interrupt sources “-” : a negative number can be represented in 2’s compliment format 0x0000 0018 LDR pc, [pc,#-0xFF0] Machine code:0xE51F FFF0 CEG2400 Ch11 Multiple Interrupts V7a