Bus-Based Computer Systems Buses. Memory devices. I/O devices: serial links timers and counters keyboards displays analog I/O © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. The CPU bus Bus allows CPU, memory, devices to communicate. Shared communication medium. A bus is: A set of wires. A communications protocol. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Bus protocols Bus protocol determines how devices communicate. Devices on the bus go through sequences of states. Protocols are specified by state machines, one state machine per actor in the protocol. May contain asynchronous logic behavior. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Four-cycle handshake device 1 enq device 1 device 2 ack device 2 1 2 3 4 time © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Four-cycle handshake, cont’d. Device 1 raises enq. Device 2 responds with ack. Device 2 lowers ack once it has finished. Device 1 lowers enq. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Microprocessor busses Clock provides synchronization. R/W is true when reading (R/W’ is false when reading). Address is a-bit bundle of address lines. Data is n-bit bundle of data lines. Data ready signals when n-bit data is ready. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Timing diagrams timing constraints: The timing constraint from A to B, for example,shows that A must go high before B becomes stable. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Bus read © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components A read or write is initiated by setting address enable high after the clock starts to rise. We set R/W 1 to indicate a read, and the address lines are set to the desired address. One clock cycle later, the memory or device is expected to assert the data value at that address on the data lines. Simultaneously, the external device specifies that the data are valid by pulling down the data ready line. This line is active low © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Bus wait state © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Bus burst read © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components In this burst read transaction, the CPU sends one address but receives a sequence of data values. We add an extra line to the bus,called burst9 here,which signals when a transaction is actually a burst. Releasing the burst9 signal tells the device that enough data has been transmitted. To stop receiving data after the end of data 4, the CPU releases the burst9 signal at the end of data 3 since the device requires some time to recognize the end of the burst. Those values come from successive memory locations starting at the given address. © 2000 Morgan Kaufman Overheads for Computers as Components

State diagrams for bus read Get data Senddata Done Release ack See ack Ack Adrs Adrs Wait Wait CPU start Device © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Bus multiplexing device data enable CPU data adrs adrs Adrs enable © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components Some buses use multiplexed address and data, as shown in Figure, Additional control lines are provided to tell whether the value on the address/data lines is an address or data. Typically, the address comes first on the combined address/data lines, followed by the data. The address can be held in a register until the data arrive so that both can be presented to the device © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. DMA Direct memory access (DMA) performs data transfers without executing instructions. CPU sets up transfer. DMA engine fetches, writes. DMA controller is a separate unit. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Bus mastership By default, CPU is bus master and initiates transfers. DMA must become bus master to perform its work. CPU can’t use bus while DMA operates. Bus mastership protocol: Bus request. Bus grant. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components What is the CPU doing during a DMA transfer? It cannot use the bus, as illustrated in Figure, if the CPU has enough instructions and data in the cache and registers, it may be able to continue doing useful work for quite some time and may not notice the DMA transfer. But once the CPU needs the bus, it stalls until the DMA controller returns bus mastership to the CPU. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. DMA operation CPU sets DMA registers for start address, length. DMA status register controls the unit. Once DMA is bus master, it transfers automatically. May run continuously until complete. May use every nth bus cycle. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Bus transfer sequence diagram © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

System bus configurations Multiple busses allow parallelism: Slow devices on one bus. Fast devices on separate bus. A bridge connects two busses. CPU slow device bridge memory slow device high-speed device © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Bridge state diagram © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components The bridge is a slave on the fast bus and the master of the slow bus. The bridge takes commands from the fast bus on which it is a slave and issues those commands on the slow bus. It also returns the results from the slow bus to the fast bus © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. ARM AMBA bus Two varieties: AHB is high-performance. APB is lower-speed, lower cost. AHB supports pipelining, burst transfers, split transactions, multiple bus masters. All devices are slaves on APB. This bus is designed to be simple and easy to implement; it also consumes relatively little power advanced high-performance bus (ahb) advanced peripheral bus (apb) © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Memory components Several different types of memory: DRAM. SRAM. Flash. Each type of memory comes in varying: Capacities. Widths. A read/write signal controls the direction of data transfer; Memory chips do not typically have separate read and write data pins. Enable- Chip Select like /Bank © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components a 256-MB memory may be available in two versions: ■ As a 64M _ 4-bit array, a single memory access obtains an 4-bit data item, with a maximum of 226 different addresses. ■ As a 32 M_ 8-bit array, a single memory access obtains a 8-bit data item, with a maximum of 225 different addresses. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Random-access memory Random-access memories can be both read and written. unlike magnetic disks, addresses can be read in any order. Dynamic RAM is dense, requires refresh periodically since the values inside the memory cells decay over time.. Synchronous DRAM is dominant type. SDRAM uses clock to improve performance, pipeline memory accesses. Static RAM is faster, less dense, consumes more power. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. SDRAM operation © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components RAS and CAS can therefore become valid at the same time SDRAMs use a separate refresh signal to control refreshing. DRAM has to be refreshed roughly once per millisecond. Rather than refresh the entire memory at once, DRAMs refresh a part of the memory at a time. When a section of memory is being refreshed, it cannot be accessed until the refresh is complete. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components SDRAMs include registers that control the mode in which the SDRAM operates. SDRAMs support burst modes that allow several sequential addresses to be accessed by sending only one address. SDRAMs generally also support an interleaved mode that exchanges pairs of bytes. Even faster synchronous DRAMs, known as double-data rate (DDR) SDRAMs or DDR2 and DDR3 SDRAMs, are now in use. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components SIMMs and DIMMs Memory for PCs is generally purchased as single in-line memory modules (SIMMs) or double in-line memory modules (DIMMs). A SIMM or DIMM is a small circuit board that fits into a standard memory socket. A DIMM has two sets of leads compared to the SIMM’s one. Memory chips are soldered to the circuit board to supply the desired memory. DIMMs (Dual In-line Memory Modules) provide a wider data path than SIMMs (Single In-line Memory Modules). DIMMs are "wider" than SIMMs in the amount of data they can carry. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Read-only memory ROM may be preprogrammed at factory. Very useful in embedded systems since a great deal of the code, and perhaps some data, does not change over time. Read-only memories are also less sensitive to radiation induced errors. factory-programmed ROM (sometimes called mask-programmed ROM) and field-programmable ROM. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components Factory-programmed ROMs are ordered from the factory with particular programming. ROMs can typically be ordered in lots of a few thousand, but clearly factory programming is useful only when the ROMs are to be installed in some quantity. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components Flash memory Non-volatile memory. Flash can be programmed in-circuit. Random access for read. Flash is dominant form of field-programmable ROM. Electrically erasable, must be block erased. Random access, but write/erase is much slower than read. uses standard system voltage for erasing and programming allowing it to be reprogrammed inside a typical system © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Flash writing Write/Erase is much slower than read. 1.6 ms write, 70 ns read. Blocks are large (approx. 1 Mb). Writing eventually causes - destroys the device. Modern lifetime approx. 1 million writes. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components the flash memory can be reprogrammed while downloading the new memory contents from a telephone line. Early flash memories had to be erased in their entirety; modern devices allow memory to be erased in blocks. Most flash memories today allow certain blocks to be protected. A common application is to keep the boot-up code in a protected block but allow updates to other memory blocks on the device. As a result, this form of flash is commonly known as boot-block flash. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Types of flash NOR flash is more flexible. NAND flash is more dense. NOR: Word-accessible read. Erase by blocks. NAND: Read by pages (512-4K bytes). NAND is cheaper, has faster erase, sequential access times. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components I/O DEVICES Some of these devices are often found as on-chip devices in micro-controllers; others are generally implemented separately but are still commonly used. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Timers and counters Timers and counters are distinguished from one another largely by their use, not by their logic. Both are built from adder logic with registers to hold the current value, with an increment input that adds one to the current register value. Very similar: a timer is incremented by a periodic clock signal; a counter is incremented by an input connected to an aperiodic signal in order to count the number of occurrences of some external event. (asynchronous, occasional signal) © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components Most counters provide both cyclic and acyclic modes of operation. In the cyclic mode, once the counter reaches the done state, it is automatically reloaded and the counting process continues. In acyclic mode, the counter/timer waits for an explicit signal from the microprocessor to resume counting. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Watchdog timer used for internal operation of a System watchdog timer is connected into the CPU bus and also to the CPU’s reset line. Watchdog timer is periodically reset by system timer. If watchdog is not reset, it generates an interrupt to reset the host. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components The CPU’s software is designed to periodically reset the watchdog timer, before the timer ever reaches its time-out limit. If the watchdog timer ever does reach that limit, its time-out action is to reset the processor. host CPU interrupt watchdog timer reset © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components A/D and D/A Converters Analog/digital (A/D) and digital/analog (D/A) converters (typically known as ADCs and DACs, respectively) are often used to interface non digital devices to embedded systems. Analog/digital conversion requires sampling the analog input before converting it to digital form. A control signal causes the A/D converter to take a sample and digitize it. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components A typical A/D interface has, in addition to its analog inputs, two major digital inputs. A data port allows A/D registers to be read and written, and a clock input tells when to start the next conversion. D/A conversion is relatively simple, so the D/A converter interface generally includes only the data value. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components keyboard A keyboard is basically an array of switches, but it may include some internal logic to help simplify the interface to the microprocessor. A switch uses a mechanical contact to make or break an electrical circuit. The major problem with mechanical switches is that they bounce A hardware debouncing circuit can be built using a one-shot timer. Software can also be used to debounce switch inputs. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components in PCs, actually contain a microprocessor to preprocess button inputs. PC keyboards typically use a 4-bit microprocessor to provide the interface between the keys and the computer. An encoded keyboard uses some code to represent which switch is currently being depressed. At the heart of the encoded keyboard is the scanned array of switches © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Switch debouncing A switch must be debounced to multiple contacts © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components Unlike a raw keyboard, the scanned keyboard array reads only one row of switches at a time. The demultiplexer at the left side of the array selects the row to be read. on a PC keyboard, the encoding must be chosen so that combinations such as control-Q can be recognized and sent to the PC. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components Another consequence is that rollover may not be allowed. For example,if you press“a,”and then press “b” before releasing “a,” in most applications you want the keyboard to send an “a” followed by a “b.” The keyboard microcontroller can be programmed to provide n-key rollover, so that rollover keys are sensed, put on a stack, and transmitted in sequence as keys are released. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components 2nd ed. Encoded keyboard An array of switches is read by an encoder. N-key rollover remembers multiple key depressions. row © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. LED Must use resistor to limit current:A resistor is connected between the output pin and the LED to absorb the voltage difference between the digital output voltage and the 0.7 V drop across the LED © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. 7-segment LCD display May use parallel or multiplexed input. A display device may be either directly driven or driven from a frame buffer. Typically, displays with a small number of elements are driven directly by logic, while large displays use a RAM frame buffer. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Types of high-resolution display Liquid crystal display (LCD) is dominant form. Plasma, OLED, etc. Frame buffer holds current display contents. Written by processor. Read by video. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Touchscreen Includes input and output device. Input device is a two-dimensional voltmeter: © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Touchscreen position sensing ADC voltage © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Digital-to-analog conversion Use resistor tree: R Vout bn 2R bn-1 4R bn-2 8R bn-3 © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Flash A/D conversion N-bit result requires 2n comparators: Vin encoder ... © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Dual-slope conversion Use counter to time required to charge/discharge capacitor. Charging, then discharging eliminates non-linearities. Vin timer © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Sample-and-hold Samples data: converter Vin © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components Memory Interfacing If we can buy a memory of the exact size we need, then the memory structure is simple. If we need more memory than we can buy in a single chip, then we must construct the memory out of several chips. We may also want to build a memory that is wider than we can buy on a single chip; for example, we cannot generally buy a 32-bit-wide memory chip. We can easily construct a memory of a given width (32 bits, 64 bits, etc.) by placing RAMs in parallel. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components We also need logic to turn the bus signals into the appropriate memory signals. For example, most busses won’t send address signals in row and column form. We also need to generate the appropriate refresh signals. © 2000 Morgan Kaufman Overheads for Computers as Components

Overheads for Computers as Components Device Interfacing Some I/O devices are designed to interface directly to a particular bus, forming glueless interfaces. But glue logic is required when a device is connected to a bus for which it is not designed. An I/O device typically requires a much smaller range of addresses than a memory, so addresses must be decoded much more finely. Some additional logic is required to cause the bus to read and write the device’s registers. © 2000 Morgan Kaufman Overheads for Computers as Components