Parallel to Serial Module

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Presentation transcript:

Parallel to Serial Module Xinyu Yi Veerasak Nichayapun

Overview Layout Synthesis P2S module simulation

Layout Syntheis Synopsis Design compiler ( tcl file) Target frequency in MHz for optimization #set my_clk_freq_MHz 10 # Delay of input signals (Clock-to-Q, Package etc.) #set my_input_delay_ns 0.1 # Reserved time for output signals (Holdtime etc.) #set my_output_delay_ns 0.1

Layout Syntheis Initial Timing Report

Layout Syntheis Post CTS Timing Report

Layout Syntheis Post-Route Timing Report

Layout Syntheis Connectivity Verify ******** Start: VERIFY CONNECTIVITY ********Start Time: Tue Jan 25 14:18:46 2011Design Name: P2S_Top_v1Database Units: 2000Design Boundary: (0.0000, 0.0000) (72.2425, 67.3100)Error Limit = 1000; Warning Limit = 50Check all netsVC Elapsed Time: 0:00:00.0Begin Summary Found no problems or warnings.End SummaryEnd Time: Tue Jan 25 14:18:46 2011 ******** End: VERIFY CONNECTIVITY ******** Verification Complete : 0 Viols. 0 Wrngs. (CPU Time: 0:00:00.0 MEM: 0.031M)

Layout Syntheis Geometry Verify ******** End: VERIFY CONNECTIVITY ******** Verification Complete : 0 Viols. 0 Wrngs. (CPU Time: 0:00:00.0 MEM: 0.031M)encounter 2> *** Starting Verify Geometry (MEM: 315.2) *** VERIFY GEOMETRY ...... Starting Verification VERIFY GEOMETRY ...... Initializing VERIFY GEOMETRY ...... Deleting Existing Violations VERIFY GEOMETRY ...... Creating Sub-Areas ...... bin size: 2080 VERIFY GEOMETRY ...... SubArea : 1 of 1 VERIFY GEOMETRY ...... Cells : 0 Viols. VERIFY GEOMETRY ...... SameNet : 0 Viols. VERIFY GEOMETRY ...... Wiring : 0 Viols. VERIFY GEOMETRY ...... Antenna : 0 Viols. VERIFY GEOMETRY ...... Sub-Area : 1 complete 0 Viols. 0 Wrngs.VG: elapsed time: 0.00Begin Summary ... Cells : 0 SameNet : 0 Wiring : 0 Antenna : 0 Short : 0 Overlap : 0 End Summary Verification Complete : 0 Viols. 0 Wrngs. **********End: VERIFY GEOMETRY********** *** verify geometry (CPU: 0:00:00.2 MEM: 4.5M)

Layout Syntheis Synthesized layout

P2S Module Simulation Three files of FSM, Shift Register and top modules are simulated in Modelsim

P2S Module Simulation Technical Problem

The End