Targeting Tiled Architectures in Design Exploration Approche de conception d’interface de communication pour les systèmes sur puce Targeting Tiled Architectures in Design Exploration Lilian Bossuet1, Wayne Burleson2, Guy Gogniat1, Vikas Anand2, Andrew Laffely2, Jean-Luc Philippe1 1 LESTER Lab Université de Bretagne Sud Lorient, France {lilian.bossuet, guy.gogniat, jean-luc.philippe}@univ-ubs.fr 2 Department of Electrical and Computer Engineering University of Massachusetts, Amherst, USA {burleson, vanand, alaffely}@ecs.umass.edu Approche de conception d’interface de communication pour les systèmes sur puce

Outline Introduction: Design Space Exploration Design Space of Reconfigurable Architecture A Target Architecture: aSoC Proposition of Design Space Exploration Flow Results Conclusion and Future Work

Design Space Exploration: Motivations Approche de conception d’interface de communication pour les systèmes sur puce Design Space Exploration: Motivations Design solutions for new telecommunication and multimedia applications targeting embedded systems Optimization and reduction of SoC power consumption Increase computing performance Increase parallelism Increase speed Be flexible Take into account run-time reconfiguration Targeting multi-granularity (heterogeneous) architectures Approche de conception d’interface de communication pour les systèmes sur puce

Design Space Exploration: Flow Approche de conception d’interface de communication pour les systèmes sur puce Design Space Exploration: Flow Progressive design space reduction: iterative exploration refinement of architecture model increase of performance estimation accuracy One level of abstraction for one level of estimation accuracy Approche de conception d’interface de communication pour les systèmes sur puce

Outline Introduction: Design Exploration Flow Principe Design Space of Reconfigurable Architecture A Target Architecture: aSoC Proposition of Design Space Exploration Flow Results Conclusion and Future Works

Reconfigurable Architectures Bridging the flexibility gap between ASICs and microprocessor [Hartenstein DATE 2001] Energy efficient and solution to low power programmable DSP [Rabaey ICASSP 1997, FPL 2000] Run Time Reconfigurable [Compton & Hauck 1999] => A key ingredient for future silicon platforms [Schaumont & all. DAC 2001]

Design Space of Reconfigurable Architecture RECONFIGURABLE ARCHITECTURES (R-SOC) FINE GRAIN (FPGA) MULTI GRANULARITY (Heterogeneous) COARSE GRAIN (Systolic) Processor + Coprocessor Tile-Based Architecture Island Topology Hierarchical Topology Coarse Grain Coprocessor Fine Grain Coprocessor Mesh Topology Linear Topology Hierarchical Topology Xilinx Virtex Xilinx Spartran Atmel AT40K Lattice ispXPGA Altera Stratix Altera Apex Altera Cyclone Chameleon REMARC Morphosys Pleiades Garp FIPSOC Triscend E5 Triscend A7 Xilinx Virtex-II Pro Altera Excalibur Atmel FPSIC aSoC E-FPFA RAW CHESS MATRIX KressArray Systolix Pulsedsp Systolic Ring RaPiD PipeRench DART FPFA

Outline Introduction: Design Exploration Flow Principe Design Space of Reconfigurable Architecture A Target Architecture: aSoC Proposition of Design Space Exploration Flow Results Conclusion and Future Works

A Target Architecture: aSoC Adaptive System-on-a-Chip (aSoC) Tiled architecture containing many heterogeneous processing cores (RISC, DSP, FPGA, Motion Estimation, Viterbi Decoder) Mesh communication network controlled with statically determined communication schedule A scalable architecture.

aSoC Architecture tile Heterogeneous Cores Point-to-point connections ctrl South Core West North East Communication Interface tile Heterogeneous Cores Point-to-point connections uProc MUL FPGA MUL

aSoC Communications Interface Interface Crossbar inter-tile transfer tile to core transfer Interconnect/Instruction Memory contains instructions to configure the interface crossbar (cycle-by-cycle) Interface Controller selects the instruction Coreports data interface and storage for transfers with the tile IP core Dynamic Voltage and Frequency Selection Dynamic Power Management Core Coreports Interface Crossbar North North South South East East West West Outputs Inputs Local Config . Local Decoder Controller Frequency & Voltage North to South & East PC Instruction Memory

aSoC Exploration ... Type of tiles Number of each type of tile Placement of the tiles Intern architecture of reconfigurable tiles (FPGA core) Communication scheduling

Outline Introduction: Design Exploration Flow Principe Design Space of Reconfigurable Architecture A Target Architecture: aSoC Proposition of Design Space Exploration Flow Results Conclusion and Future Work

Design Space Exploration: Goals Approche de conception d’interface de communication pour les systèmes sur puce Design Space Exploration: Goals Goal: Rapid exploration of various architectural solutions to be implemented on heterogeneous reconfigurable architectures (aSoC) in order to select the most efficient architecture for one or several applications Take place before architectural synthesis (algorithmic specification with high level abstraction language) Estimations are based on a functional architecture model (generic, technology-independent) Iterative exploration flow to progressively refine the architecture definition, from a coarse model to a dedicated model Approche de conception d’interface de communication pour les systèmes sur puce

Design Exploration Flow Targeting Tiled Architecture SPECIFICATION C to HCDFG parser Function F 2 HCDFG Graphs of the application Application App 1 Model of the aSOC Architectures Tile T aSOC A Analysis Tile Exploration Results of the Tile exploration step Performance 11 , C , Occ 21 12 22 Builder Static Communication Scheduling Final model of aSOC architecture THF Model HF Model

Application Analysis Use of algorithmic metrics and dedicated scheduling algorithms to highlight the target architectures Algorithmic metrics: Characterize the application orientation Processing Memory Control Characterize the application potential parallelism

Tile Exploration: with 3 steps Projection: Link between necessary resources (application) and available resources (tile) Use of an allocation algorithm based on communication costs reduction Composition: Take into account of the function scheduling to estimate additional resources (register, mux, …) Estimation: performance interval computation (lower and upper bounds) speed/resource utilization/power characterization

aSoC Builder Environment AppMapper Partition and assignment Approche de conception d’interface de communication pour les systèmes sur puce aSoC Builder Environment AppMapper Partition and assignment based on Run Time Estimation Compilation Communication Scheduling Core compilation Generate tiles configuration Communications instructions Bitstreams (for reconfigurable tile) RISC instructions Approche de conception d’interface de communication pour les systèmes sur puce

aSoC Analysis Use the results of previous steps Approche de conception d’interface de communication pour les systèmes sur puce aSoC Analysis Use the results of previous steps Functions scheduling Tile allocation Communication scheduling Complete estimation of the proposed solution Global execution time Global power consumption Total area Approche de conception d’interface de communication pour les systèmes sur puce

Outline Introduction: Design Exploration Flow Principe Design Space of Reconfigurable Architecture A Target Architecture: aSoC Proposition of Design Space Exploration Flow Results Conclusion and Future Work

Results aSoC architecture (UMASS) AppMapper (UMASS) Prototype of aSoC interconnect Technology 0.18 µm Clock speed of 400 MHz AppMapper (UMASS) Several mapped applications Matrix operations Median Filter Viterbi decoder DCT Tile exploration (UBS) Application analysis Intelligent Camera (motion detection) Matching Pursuit Projection step Lee DCT Matrix operations

Outline Introduction: Design Exploration Flow Principe Design Space of Reconfigurable Architecture A Target Architecture: aSoC Proposition of Design Space Exploration Flow Results Conclusion and Future Work

Conclusion and future work Original design exploration flow working at a high level of abstraction Fast and flexible (use of functional view of the architectures) Targeting an efficient reconfigurable architecture: aSoC Statically-scheduled, point-to-point communications Future Work Development of larger set of design exploration benchmarks Exploration of other configurable systems

Thank you ...

Approche de conception d’interface de communication pour les systèmes sur puce Previous Work Xplorer - University of Kaiserslautern, Germany [Hartenstein PATMOS 2000] Targets a mesh coarse grain architecture: The KressArray a fast reconfigurable ALUs Gives design guidance concerning: the size of the array, the available operators, the communication architecture and the connection structure. Controlled by performance and power estimations. Starts with high level specification of application (ALE-X language). RAW - Massachusetts Institute of Technology, USA [Moritz FCCM 1998] Targets a reminiscent coarse grained FPGA: The MIT Raw Microprocessor Answers to the balance problem: to determine the best division of VLSI resources among computing, memory and communication. Answers to the grain problem: to determine the optimum size of each architecture tiles Use several models: architecture model, costs model and performance model Approche de conception d’interface de communication pour les systèmes sur puce

HCDFG: Hierarchical Control Data Flow Graph Loop CORE X Y# C Y MAC ALU A Task 1 Task 2 F2 F1 F5 F4 F3 HCDFG HDFG LOOP DFG CDFG

Application’s Metrics Y. Le Moullec, N. Ben Amor, J-Ph. Diguet, M. Abid and J-L. Philippe. Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. In DATE 2002, Munich, Germany, March 2002 Average Parallelism metric (a lot of parallelism if γ is high) Nb of global memory accesses and processing operations Critical Path γ = Nb of global memory accesses Nb of processing operations + Nb of global memory accesses MOM = Memory Orientation Metric [0,1] Nb of test Nb of global mem. accesses + Nb of proc. op. + Nb of test COM = Control Orientation Metric [0,1]