An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, and Patrick McNamara PDF Solutions Inc. DAC 2005, Anaheim, CA

Technology Roadmap Challenges 45nm Lithography Layout pattern dependence Immersion litho, OPC/PSM integration w/ photo window Front end/Transistor New gate/oxide architectures Reliability 65nm Lithography OPC/PSM integr. w/ photo-window Front-end/Transistor Layout dependent performance Parametric variation 90nm Back-end integration Low-k CMP Product ramp issues Yield vs. performance Look at road map, lots of new materials and process changes, each introduces some unknown process-design interaction

The Evolution of Product Yields Now we find that the yield is more driving by these process-design interactions more than just random failures Random defects are no longer the dominant yield loss mechanism Yields are limited by design features

From Reactive to Proactive DFM: A Copernican Revolution… Yield Revolved Around Rules Design rules guarantee yield!…well, not really… …then recommended rules …and opportunistic design data base post-processing to enforce them People have responded by making more extended design rules. However these rules clash and still don’t assure yields. So, what folks need to do is to move to yield simulation. Yield Models are the driving force in the DFM universe Accurate Yield Models Characterized in Silicon Fully integrated in standard design tools and flows

Rule-based DFM? 32 FPB 25 FPB 20 FPB 19 FPB MUX4X1AFY_Y1 - 20 tracks MUX4X1AFY_COY4 - 25 tracks MUX4X1AFY_PMSY4 - 21 tracks This cell represents a cell that you might design using minimum design rules. # Here is an alternative that you could get with recommended design rules. Now, without PDfx, the designer has to make a choice right up front, will I construct my design using all small cells, and hope I get some yield, or all big cells, and hope the device is small enough to be viable. # PDfx suggests that in addition to these, you can add a couple more variants. These don’t have the full robustness of the monster cell, but they use limited space efficiently to tackle particular yield loss mechanisms and get the highest yield possible in limited space. But how do you choose amongst these? # With the yield ratings supplied by PDF, now the EDA tool can make an informed tradeoff. In fact, the cell on the left achieves a 22% yield improvement for only one extra track. And the cell on the right achieves a further 20% at the cost of 4 track. The monster cell, saves only one failure in a billion and is probably not worth the space involved. PDFX gives you choices and the information to make them right. MUX4X1AFY1_Y16 - 27 tracks

Reactive vs. Proactive DFM Reactive DFM Synthesis Place&route Design IP lib. Design Floorplan Verification Timing & SI Physical Formal DFM sign-off DFM & Manufacturing OPC/RET Dummy Fill MDP DFM Optimizations Mask Making DRM Verification Design SPICE Pro-Active DFM What is the history of DFM/DFY. Well, today most folks think about yield at the end of the flow, when they are doing fill, opc, via insertion, etc. At that point you are past when the design team that understood the intent is involved. This is breaking for a few reasons: 1. Past timing and electrical verification, how do you know you have not messed up the performance of the device? 2. At this stage of the flow, if you have a layout that is inherently more difficult to OPC, how do you fix it w/o losing the designers intent? Something has to change, we need to be able to have the designers who are at the front end of the physical design and ideally at the system design account for yield and manufacturability. They have the most degrees of freedom. However, being the further in time from when the design is actually manufactured, how do they use it? Manufacturing Facility Yield –aware Synthesis Yield-aware Place&route Design IP lib. Design Yield Aware Floorplan Verification Statistical Timing & SI Physical Formal DFM sign-off DFM & Manufacturing OPC/RET Dummy Fill MDP DFM Tuning Mask Making DRM Verification Design SPICE

Proactive DFM Designer access to process data is limited DFM today is Reactive Increased design cycle time Risky design feature changes Misaligned mask GDSII and design database DFM needs to be Proactive Up-front accurate process characterization Occurring early in the design flow Model based IP characterization Manufacturable-by-construction designs

DFM characterization Of IP libraries Library GDS Process FR (D0,l) Yield Extractions Design Attributes ACC .pdfm Process Margins and Litho calibration data Lithography Simulator Library YIMP Context Generation Golden OPC/RET RANDOM Design SYSTEMATIC Litho Process Window Characterize IP library for yield (.pdfm) Extract design attributes of yield models Include random, design systematic and litho effects New yield library view (.pdfm) Enable hierarchical large capacity DFM chip analysis

Random Yield Loss: Physical Mechanisms Material opens Material shorts Type Yield Loss Mechanisms Random Active, poly and metal shorts and opens due to particle defects Contact and via opens due to formation defectivity

Random Yield Loss: Test Structures Extract Metal layer open and short defectivity Extract Metal layer open and short Defect Size Distribution (DSD)

Systematic Yield Loss: Physical Mechanisms Type Yield Loss Mechanisms Systematic Impact of micro/macro loading design rule marginalities Leakage from STI related stress Contact/via opens due to local neighborhood effects (e.g. pitch/hole size) Misalignment, line-ends/borders

Systematic Yield Loss: Test Structures Without Neighborhood With Neighborhood STI M1 To Pad A To Pad B To Pad C N+ PWL P+

Printability Yield Loss: Physical Mechanisms Type Yield Loss Mechanisms Systematic Poor contact coverage due to misalignment and defocus/pull back Poly/Metal shorts Material opens

Printability Yield Loss: Modeling Layout Metric Misalignment Mask Error Defocus Exposure Yield Loss coverage

The .pdfm View Library characterized to generate manufacturability view (.pdfm) Random and design systematic yield Litho process window Using calibrated yield models Multi-layer litho process window incorporated Cell Characteristic Library View Lay out GDS Schematic SPICE Netlist P&R Footprint LEF Performance .lib Logic Function Verilog Power Noise … Manufacturability .pDFM

Application: IP library DFM Quality Analysis Yield sensitivity analysis Optimal design depends on process corner Ex NAND2: Y5, Y6, Y1, Y4 Best becomes worst at different process corner Ex NAND2: Y1_m1opens vs. Y1_m1shorts DFM Sensitivity depends on layout attributes M1 more sensitive than Poly Identify redundant layout implementations Ex AOI: Y4, Y5 COAO3BTC2NOR2XC_R2 -6 -4 -2 2 4 6 8 10 Process Corner Cell FR Improvement (ppb) orig Y1 Y2 Y3 Y4 Y5 Y6 NAND2 CELL Poly Open Poly Short M1 Open M1 Short Dominant Process Effect AOI CELL Poly Open Poly Short M1 Open M1 Short Process Corner

Yield aware synthesys and place&route RTL Design VERIFICATION Hierarchical Floorplan DFM SW plug-ins Yield View (.pdfm) Yield Gap Yield Yield Models Models Estimation Estimator Physical Synthesis Yield Yield DFM LIBRARIES Extended IP Optimization Optimizer Chip Assembly Sign-off Standard Libraries Proactive DFM Maximize manufacturability by construction

Conclusions Impact of design systematic and lithography yield loss mechanisms crossed over random phenomena Rule-based, reactive DFM is impractical Model-based, proactive DFM is the answer Early in the design flow Find the best trade-off based on actual process capabilities Before verification