Chapter 1 Fundamentals of Computer Design

Slides:

Advertisements

Similar presentations

Computer Organization and Architecture

Advertisements

Computer Organization Lab 1 Soufiane berouel. Formulas to Remember CPU Time = CPU Clock Cycles x Clock Cycle Time CPU Clock Cycles = Instruction Count.

Chapter 8: Central Processing Unit

1 Lecture 3: Instruction Set Architecture ISA types, register usage, memory addressing, endian and alignment, quantitative evaluation.

RISC / CISC Architecture By: Ramtin Raji Kermani Ramtin Raji Kermani Rayan Arasteh Rayan Arasteh An Introduction to Professor: Mr. Khayami Mr. Khayami.

CSE 340 Computer Architecture Spring 2014 MIPS ISA Review

Performance Evaluation of Architectures Vittorio Zaccaria.

Chapter 6 สถาปัตยกรรมไมโครโพรเซสเซอร์แบบต่างๆ Processor Architectures

Computer Organization and Architecture 18 th March, 2008.

RISC vs CISC CS 3339 Lecture 3.2 Apan Qasem Texas State University Spring 2015 Some slides adopted from Milo Martin at UPenn.

CSCE 212 Chapter 4: Assessing and Understanding Performance Instructor: Jason D. Bakos.

COMP381 by M. Hamdi 1 Instruction Set Architectures.

Chapter XI Reduced Instruction Set Computing (RISC) CS 147 Li-Chuan Fang.

5.2 Mathematical Power, Convenience, and Cost The set of operations represents a tradeoff among the cost of the hardware, the convenience for a programmer,

Computer Architecture Lecture 2 Instruction Set Principles.

Microprocessors Introduction to RISC Mar 19th, 2002.

RISC. Rational Behind RISC Few of the complex instructions were used –data movement – 45% –ALU ops – 25% –branching – 30% Cheaper memory VLSI technology.

Cisc Complex Instruction Set Computing By Christopher Wong 1.

Processor Organization and Architecture

COMPUTER ORGANIZATIONS CSNB123 May 2014Systems and Networking1.

CH13 Reduced Instruction Set Computers {Make hardware Simpler, but quicker} Key features  Large number of general purpose registers  Use of compiler.

RISC:Reduced Instruction Set Computing. Overview What is RISC architecture? How did RISC evolve? How does RISC use instruction pipelining? How does RISC.

1 CHAPTER 2 THE ROLE OF PERFORMANCE. 2 Performance Measure, Report, and Summarize Make intelligent choices Why is some hardware better than others for.

Computer architecture Lecture 11: Reduced Instruction Set Computers Piotr Bilski.

1 (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd Ed., Morgan Kaufmann,

Chapter 8 CPU and Memory: Design, Implementation, and Enhancement The Architecture of Computer Hardware and Systems Software: An Information Technology.

Chapter Six Sun SPARC Architecture. SPARC Processor The name SPARC stands for Scalable Processor Architecture SPARC architecture follows the RISC design.

Instruction Set Architecture The portion of the machine visible to the programmer Issues: Internal storage model Addressing modes Operations Operands Encoding.

Chapter 1 Performance & Technology Trends Read Sections 1.5, 1.6, and 1.8.

Computer Organization and Architecture Instructions: Language of the Machine Hennessy Patterson 2/E chapter 3. Notes are available with photocopier 24.

Ted Pedersen – CS 3011 – Chapter 10 1 A brief history of computer architectures CISC – complex instruction set computing –Intel x86, VAX –Evolved from.

RISC and CISC. What is CISC? CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and which make efficient use.

Differences in ISA Instruction length

MIPS Processor Chapter 12 S. Dandamudi To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer,

CPU Performance using Different Parameters CS 250: Andrei D. Coronel, MS,CEH,PhD Cand.

ECEG-3202 Computer Architecture and Organization Chapter 7 Reduced Instruction Set Computers.

Pipelining and Parallelism Mark Staveley

Performance Enhancement. Performance Enhancement Calculations: Amdahl's Law The performance enhancement possible due to a given design improvement is.

Performance Performance

COMPUTER ORGANIZATIONS CSNB123 NSMS2013 Ver.1Systems and Networking1.

EECS 322 March 18, 2000 RISC - Reduced Instruction Set Computer Reduced Instruction Set Computer  By reducing the number of instructions that a processor.

DR. SIMING LIU SPRING 2016 COMPUTER SCIENCE AND ENGINEERING UNIVERSITY OF NEVADA, RENO CS 219 Computer Organization.

ISA's, Compilers, and Assembly

Computer Engineering Rabie A. Ramadan Lecture 2. Table of Contents 2 Architecture Development and Styles Performance Measures Amdahl’s Law.

Chapter 13 RISC Peter Wong CS147 Fall2010. What is RISC? RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes.

RISC / CISC Architecture by Derek Ng. Overview CISC Architecture RISC Architecture  Pipelining RISC vs CISC.

CC410: System Programming Dr. Manal Helal – Fall 2014 – Lecture 3.

Addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine.

Performance. Moore's Law Moore's Law Related Curves.

Topics to be covered Instruction Execution Characteristics

Software Architecture in Practice

Lecture 3: MIPS Instruction Set

Immediate Addressing Mode

ECE 4100/6100 Advanced Computer Architecture Lecture 1 Performance

Visit for more Learning Resources

Overview Introduction General Register Organization Stack Organization

An example of multiplying two numbers A = A * B;

CISC (Complex Instruction Set Computer)

CSCE 212 Chapter 4: Assessing and Understanding Performance

Defining Performance Section /14/2018 9:52 PM.

Central Processing Unit

CISC AND RISC SYSTEM Based on instruction set, we broadly classify Computer/microprocessor/microcontroller into CISC and RISC. CISC SYSTEM: COMPLEX INSTRUCTION.

EE 445S Real-Time Digital Signal Processing Lab Spring 2014

Lecture 3: MIPS Instruction Set

Arrays versus Pointers

Chapter 12 Pipelining and RISC

Lecture 4: Instruction Set Design/Pipelining

Presentation transcript:

Chapter 1 Fundamentals of Computer Design

Review Performancex = X is n times faster than Y Increasing performance decreases execution time. CSCE 614 Fall 2009

Review CPU Execution time = MIPS = CSCE 614 Fall 2009

Amdahl’s Law The performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used. Speedup = CSCE 614 Fall 2009

Amdahl’s Law Fraction enhanced: the fraction of the computation time that can be enhanced. Speedup enhanced: the improvement gained by the enhanced execution mode. CSCE 614 Fall 2009

Example (Amdahl’s Law) Suppose we want to enhance the processor used for Web serving. The new CPU is 10 times faster in Web serving. Assuming that the original CPU is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup? CSCE 614 Fall 2009

Example (Performance Eq.) Suppose we have the followings: Freq. of FP op (other than FPSQR): 25% Avg. CPI of FP op: 4.0 Avg. CPI of other instructions: 1.33 Freq. of FPSQR: 2% CPI of FPSQR: 20 Assume that the two design alternatives are to decrease the CPI of FPSQR to 2 or decrease the avg. CPI of all FP operations to 2.5. Compare these two design alternatives. CSCE 614 Fall 2009

Instruction Set Architecture The portion of the computer visible to the programmer or compiler writer. RISC Architecture (MIPS, PowerPC, SPARC) CISC Architecture (IBM 360/370, VAX) Intel 80x86 Internally uses RISC instruction set. Externally supports an 80x86 instruction set. CSCE 614 Fall 2009

RISC Architecture Philosophy Characteristics Simple load-store architecture Fixed format Efficient pipelining CSCE 614 Fall 2009

RISC vs. CISC Pipelining Ease of Hardware Implementation Simple Instructions Simple Addressing Mode Fixed-Length Formats Large Number of Registers MIPS, … Simple Compilers Powerful Addressing Mode Powerful Instructions Efficient Instruction Encoding Few Registers VAX CSCE 614 Fall 2009