ADC12J4000, TSW14J10, VC707 Testing.

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Presentation transcript:

ADC12J4000, TSW14J10, VC707 Testing

Test Setup: Single tone is given as input to the device. Test conditions: Fs = internal 4GHz, serdes = 8Gbps Fin = 551MHz LMK = 2GHz, clock dist mode VC707 Ref clock = 400MHz VC707 Core clock = 200MHz

On ADC GUI, load the values as shown below

In Low Level View tab, set LMK04828 address 0x110 to 0x05 (div by 5) to set VC707 REFCLK = 400MHz

In Low Level View tab, set LMK04828 address 0x100 to 0x0A (div by 10) to set VC707 Core CLK = 400MHz

Open HSDCD Pro, select “ADC12J4000_BYPASS”, Enter “4G” for ADC Output Data Rate

Capture results using a 550MHz input tone