Hardware Considerations Chapter 2,3 9/20/2018

Topics Hardware consideration – Chapter 2 9/20/2018

XINU and Router Xinu is a small, elegant system that follows a hierarchical structure. http://en.wikipedia.org/wiki/Xinu Wireless router: Access points, wireless communication WRT54GL: Wireless broadband router Link Embedded Xinu Its goal is to port the XINU Operating System to the MIPS platform by specifically targeting LinkSys WRT54GL routers. http://xinu.mscs.mu.edu/ 9/20/2018

WRT54GL: Wireless router from Linksys Firmware running the operations Need to communicate with the firmware Load OpenWRT/XINU or other home brewed code into the router Need basic access through a serial port to the firmware Need console access to the firmware That is the purpose of the hardware update. 9/20/2018

Project 1: Load Embedded XINU into WRT54GL wireless router We create a little computer out of WR54GL by loading embedded XINU in to its RAM. Assemble the components needed to add a UART chip to the WRT54GL that will enable you to access WRT54GL storage and devices. Obtain a cross-compiler to compile embedded XINU kernel into MIPS code for the CPU on WRT54GL. We have downloaded a Linux-based cross-compiler that will compile the embedded XINU files and generate xinu.boot or variations of this. Download embedded xinu tar ball and untar it and compile it (gmake) to obtain it to generate the xinu.boot Lets study the various components of the embedded XINU distribution. 9/20/2018

AUTHORS include/ LICENSE README system/ Once you have downloaded and extracted the xinu tarball, you will see a basic directory structure: AUTHORS include/ LICENSE README system/ tty/ compile/ lib/ loader/ shell/ test/ uart/ AUTHORS is a brief history of contributors to the XINU operating system in it's varying iterations. compile/ contains the Makefile and other necessities for building the XINU system once you have a cross-compiler. include/ contains all the header files used by XINU. lib/ contains a folder (libxc/) with a Makefile and source for the library, as well as a binary blob which contains the pre-compiled library. LICENSE is the license under which this project falls. loader/ contains assembly files and is where the bootloader will begin execution of O/S code. README is this document. shell/ contains the source for all shell related functions. system/ contains the source for all system functions such as the nulluser process (initialize.c) as well as code to set up a C environment (startup.S). test/ contains a number of testcases (which can be run using the shell command testsuite). tty/ contains the source for the tty driver. uart/ contains the source for the uart driver. 9/20/2018

Next steps Connect the serial port of the modified hardware to the serial port of a host computer with xinu.boot code. Use a serial communication program (say using a Hyperterminal) to configure the serial port of the host to the settings: 8 data bits, no parity bit, and 1 stop bit (8N1) with a speed of 115,200 bps. Use another router to form a local network and assign IP addresses to the router and the host computer. Power up the WRT54GL. If you send cntrlC (break) characters from host console, you will see it responding with CFE> (common firmware environment for WRT54GL) The Broadcom Common Firmware Environment (CFE) is a collection of software modules for initialization and bootstrap of designs incorporating Broadcom MIPS64™ processors. Link Serial port you created is your means to communicate with WRT54GL CFE Use a TFTP on the host to make the boot images available on the network for XINU to boot. (How?) ifconfig eth0 –auto (obtain ip address for eth0 of WRT54GL) boot -elf [host ip]:xinu.boot (initiate a TFTP boot) Above two commands are given from CFE command line Once XINU boots (uploads into the RAM), you will see XINU shell. Now you can run XINU commands: help, ps etc. Add a simple C program hello.c to print “hello world”. 9/20/2018

Hardware Basics Von Neumann Architecture Hardware interfacing Latching: recording the appearance of a signal for later processing Edge vs. level triggering Tristate logic: high, low, tristated Wait state System interfaces and buses: address, data, control Universal asynchronous synchronous relay terminal (UART) is typically used for parallel to serial transfer 9/20/2018

Standard Interfaces MIL-STD-1553B Small Computer system interface (SCSI) IEEE 1394 firewire 9/20/2018

MIL-STD-1533B Widely used in military and commercial avionics Specifies hardware configuration and transmission and receipt protocols 1533-bus protocol is a master-slave protocol: one module on the bus acts as a master and others as slaves and respond to master’s commands. Coupling of the devices is such that one device failure does not affect the others. Master puts out device number followed by the packets to that device. Also standard provides specification for handling of failure of the master. 9/20/2018

SCSI (“Scuzzy”) Parallel interface to many devices SCSI 1, 2, 3, narrow, wide, fast , ultra, ultra-2, ultra-160 SCSI supports daisy chained devices SCSI supports Fiber Channel and Firewire besides familiar ribbon cable Daisy chained devices can communicate independently Device 0 is the boot device and other devices get non-0 id. Examples: interfaces to hard drive, CDROMs, scanners and other peripherals 9/20/2018

IEEE 1394 Firewire Standard specifies very fast external bus that supports data transfer rates of up to 400 megabits per sec. (1394a) and 800 Mbps in 1394b. Apple developed the technology Can connect up to 63 devices Multiple speeds on single bus, thus avoiding daisy chaining and peer-peer Hot pluggable: devices can be added and removed when the bus is active Two types of transfer: asynchronous and isochronous Isochronous: data transfer at predetermined rate; multimedia applications; used in cameras, VCRs, televisions, audio devices 9/20/2018

Memory Technologies Ferrite core (dinosaur of memories) Semiconductor memory (RAM) Fusible link: ROM and nonvolatile; UVROM: ultra violet erasable ROM EEPROM: Electronically erasable PROM Flash memory: rewritable PROM that uses single transistor per bit; commonly used in embedded real-time applications. Ferroelectric RAM: 40ns access times, 64 Mbyte arrays. 9/20/2018

Memory organization and map FFFFFFFF Devices: DMA Devices: memory mapped IO Calibration constants: EEPROM Stack, heap, variables: RAM Fixed Data: EPROM Program: PROM FFFFFF00 FFFFFE00 FFC00000 E0000F00 E0000000 00000000 9/20/2018

Input/output Programmed input/output: an IN instruction will transfer data from input device to a CPU register. An OUT instruction does the opposite. Example: to control the speed of a motor (controller) connected to system in the device space as programmed IO: LOAD R1, &speed LOAD R2, &motoraddress OUT 9/20/2018

Direct memory access (DMA) When using a DMA, access to the computer’s memory is given other devices in the system without CPU intervention. Lets discuss its circuitry and operation. 9/20/2018

Memory mapped IO Does not require special IN and OUT operation. Certain designated locations of memory appear as virtual IO ports. For controlling the speed of a stepper motor: LOAD R1, &speed STORE R1, &motor_address Where speed is a bit mapped command Bit 0: light on Bit 1..3: control other devices Bit 4..7: stepper motor speed (4 bits for 16 different speeds) 9/20/2018

Interrupts Interrupts are signals generated to indicate exceptional events. Internal and external interrupts Instruction support for interrupts: enable and disable interrupts Internal CPU handling of interrupts: Current state including PC is saved and the control is transferred to ISR (interrupt service routine). What to do when dealing with multiple external devices all working asynchronously with the CPU? Use a programmed interrupt controller (PIC). 9/20/2018

Enhancing Performance Exploit locality of reference: paging; heavily used cell phones and networked handheld devices Cache recent computations, current data set, current locality of instructions Pipelining: used in RISC processors Coprocessors for special processing: digital signal processing (DSP), fast Fourier transforms (FFT), etc. 9/20/2018

Transducers Transducers are devices that convert energy from one form to another. Temperature sensors (or any sensor) Accelerometer: compression of piezoelectric device is exploited to convert the compression of an electrical signal. Position resolvers A/D converters 9/20/2018

Kernel & Device drivers Servers (application ~, web ~, component ~) Shell XWin Thread lib ftp User applications System call interface Process, memory, file system, network managers. Kernel Device drivers Hardware/controller Devices 9/20/2018

Real-time Kernels A process is an abstraction of a running program and a logical unit of work scheduled by the operating system. A thread is a light weight process that represents of a flow of control thorough a process. Real-time operating system must provide these specific functions for processes: Scheduling Dispatching Intercommunication and synchronization Kernel of an operating system provides these functions. 9/20/2018

Simple kernels Polled loop: Say a kernel needs to process packets that are transferred into the DMA and a flag is set after transfer: for(;;) { if (packet_here) { process_data(); packet_here=0; } Excellent for handling high-speed data channels, a processor is dedicated to handling the data channel. Disadvantage: cannot handle bursts 9/20/2018

Simple kernels: cyclic executives Illusion of simultaneity by taking advantage of relatively short processes in a continuous loop: for(;;) { process_1(); process_2(); process_3(); … process_n(); } Different rate structures can be achieved by repeating tasks in the list: 9/20/2018

Cyclic Executives: example: Interactive games Space invaders: for(;;) { check_for_keypressed(); move_aliens(); check_collision(); update_screen(); } check_keypressed() checks for three button pressings: move tank left or right and fire missiles. If the schedule is carefully constructed we could achieve a very efficient game program with a simple kernel as shown above. 9/20/2018

Finite state automata and Co-routine based kernels void process_a(void){ for(;;) { switch (state_a) { case 1: phase_a1(); | case 2: phase_a2(); | …. case n: phase_an();}}} void process_b(void){ switch (state_b) { case 1: phase_b1(); | case 2: phase_b2(); | case n: phase_bn();}}} state_a and state_b are state counters; Communication between coroutines thru’ global variables; Example: the fanous CICS from IBM : Customer Information Control System IBM’s OS/2 uses this in Windows presentation management. 9/20/2018

Interrupt driven systems Main program is a simple loop. Various tasks in the system are schedules via software or hardware interrupts; Dispatching performed by interrupt handling routines. Hardware and software interrupts. Hardware: asynchronous Software: typically synchronous Executing process is suspended, state and context saved and control is transferred to ISR (interrupt service routine) 9/20/2018

Interrupt driven systems: code example void main() { init(); while(TRUE); } void int1(void){ save (context); taks1(); retore (context);} restore (context);} Foreground/background systems is a variation of this where main does some useful task in the background; 9/20/2018

Process scheduling Scheduling is a very important function in a real-time operating system. Two types: pre-run-time and run-time Pre-run-time scheduling: create a feasible schedule offline to meet time constraints, guarantee execution order of processes, and prevents simultaneous accesses to shared resources. Run-time scheduling: allows events to interrupt processes, on demand allocation of resources , and used complex run-time mechanisms to meet time constraints. 9/20/2018

Task characteristics of real workload Each task Ti is characterized by the following temporal parameters: Precedence constraints: specify any tasks need to precede other tasks. Release or arrival time: ri,j: jth instance of ith task Phase Φi: release time of first instant of ith task Response time: time between activation and completion Absolute deadline: instant by which task must complete Relative deadline: maximum allowable response time Period Pi: maximum length of intervals between the release times of consecutive tasks. Execution time: the maximum amount of time required to complete a instance of the task assuming all the resources are available. Lets look at some examples next week. 9/20/2018

Summary We studied hardware considerations for embedded and real time systems. Hardware choices and design of the various controllers have significant effect on the performance of a RT embedded systems. 9/20/2018