Other DataPath designs: Microprogrammed and pipelined datapaths Laxmikant Kale http://charm.cs.uiuc.edu Parallel Programming Laboratory Department of Computer Science University of Illinois at Urbana Champaign 9/20/2018 cs231Kale

Problems with our datapath Other than the obvious: need more registers, more bits in each register (and therefore in datapath) The clock cycle time is contrained by the longest possible instruction execution time. Solution: break an instruction execution into multiple cycles Bucket brigade: pipelined datapath Microprogrammed datapath Access PC 1 ns Instruction Memory 4 ns Register read 3 ns MUX B ALU or Memory MUX D Register write 9/20/2018 cs231Kale

A Microprogrammed Datapath The datapath we worked with for the past few weeks was just an example We will look at another datapath today To emphasize that alternate designs are possible To show an example where each instruction takes multiple cycles to finish To show a different way of generating control signals Material is not based on the book Used to be in the older version.. For the exam: Basic understanding of the slides, and section 8-7 (of the 3rd edition) Follow the web link there if you are interested 9/20/2018 cs231Kale

Why multiple cycles? Wouldn’t it be slower? Not necessarily: if each clock cycle can be made shorter Variable number of cycles for instructions (some 2, some 5) 9/20/2018 cs231Kale

Let us use one memory module New Datapath Let us use one memory module for both data and instructions Allow for multiple cycles for each instruction 9/20/2018 cs231Kale

IR: Instruction Register PC IR: Instruction Register Register File MUX B MUX M ALU Memory Data In Address Data Out MUX D 9/20/2018 cs231Kale

How to generate contol signals Consequence of this datapath: Needs a cycle to fetch instruction from memory Control word: the set of control signals In our older datapath: Control word was determined fully by the instruction Here: It depends on instruction and on which cycle within the instruction we are in Example: 9/20/2018 cs231Kale

Generating control: sequential circuit IR: Instruction Register Control Unit Control word Cycle Counter 9/20/2018 cs231Kale

Generating Control:Microprogram Memory IR: Instruction Register Microprogram Memory Control word Next MicroInstruction Address MicroProgram Counter 9/20/2018 cs231Kale

9/20/2018 cs231Kale

Pipelined datapath Simplified scenario: 4 step assembly line Instruction Fetch Operand Fetch Execution of operation Writeback Although total time for each instruction to finish is the same (or slightly larger) The unit as a whole processes more instructions per unit time Just as in assembly of a car More on this in CS 232 and beyond 9/20/2018 cs231Kale