Digital Signal Processors DSP Processors Digital Signal Processors Group#13 4\3\2012

Outlines DSP processors Architecture Data handling Program flow Programming Applications

Outlines DSP processors Architecture Data handling Program flow Programming Applications

DSP processors A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing. DSP is the application of mathematical operations to digitally represent signals. The source of these signals can be Audio Image

DSP processors Digital signal processing enjoys several advantages over analog signal processing: DSP systems are able to accomplish tasks inexpensively that would be difficult or even impossible using analog electronics. (Examples of such applications include speech synthesis and speech recognition). Insensitivity to environment. Insensitivity to component tolerances. Repeatable behavior. Re-programmability. Size. 9/20/2018

Instruction types Arithmetic and Multiplication Logic Operations (add, subtract, increment, decrement, negate, round, absolute value) and multiplication. With the exception of the Texas Instruments TMS320Clx processor provide multiply-accumulate instructions as well. Logic Operations and, or, exclusive-or, and not. Shifting Arithmetic (left and right). Logical (left and right). 9/20/2018

Instruction types(Cont.) Rotation Left. Right. Comparison Most processors provide a set of status bits (ex: zero-Bit, minus Bit and overflow Bit) that provide information about the results of arithmetic operations. used in conditional branches or conditional execution instructions. Looping Subroutine Calls may be called jump-to-subroutine instructions. 9/20/2018

Instruction types(Cont.) Branching jump or got o instructions on some processors. Conditional Un-conditional 9/20/2018

Instruction types(Cont.) Branching (cont.) Delayed Multicycle 9/20/2018

Outlines DSP processors Architecture Data handling Program flow Programming Applications

Architecture Instruction sets A basic DSP processor supports RISC (Reduce Instruction Set Computers) and CISC (Complex Instruction Set Computers) instructions. Single instruction, multiple data (SIMD) Instruction-level parallelism (ILP) 9/20/2018

Architecture (cont.) Single instruction, multiple data (SIMD) Single instruction, multiple data describes computers with multiple processing elements that perform the same operation on multiple data simultaneously.

Architecture (cont.) Instruction-level parallelism (ILP) Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously. Ex: 1. e = a + b 2. f = c + d  independent 3. g = e * f ILP allows the compiler and the processor to overlap the execution of multiple instructions or even to change the order in instructions

Architecture of the Digital Signal Processor Transferring information to and from memory includes data, such as samples from the input signal and the filter coefficients, as well as program instructions, the binary codes that go into the program sequencer. Ex. a  b×a 9/20/2018

Architecture of the DSP(cont.) There are mainly three types of architectures employed for the processors: Von Neumann architecture Harvard architecture Super Harvard Architecture 9/20/2018

1-Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). For example, Memory (instruction and data) add. bus CPU data bus a  b×a 9/20/2018

1-Von Neumann architecture(cont.) Advantages: This type of architecture is cheap, and Simple to use because the programmer can place instructions or data anywhere throughout the available memory. Disadvantages: Von Neumann computers spend a lot of time moving data to and from the memory, and his slows the computer. 9/20/2018

2- Harvard architecture Separate memories for data and program instructions, with separate buses for each. For example, Program Memory (instruction only) PM add. bus CPU DM add. bus Data Memory (data only) PM data bus DM data bus a  b×a 9/20/2018

2- Harvard architecture(cont.) Advantages: Since the buses operate independently, program instructions and data can be fetched at the same time, improving the speed over the single bus design. Disadvantages: data memory bus is busier than the program memory bus. 9/20/2018

3- Super Harvard Architecture Improves upon the Harvard design by adding an instruction cache and dedicated I/O controller. For example, Program Memory (instruction and secondary data) PM add. bus CPU DM add. bus Data Memory (data only) PM data bus Instruction Cache DM data bus I/O Controller a  b×a Data 9/20/2018

3- Super Harvard Architecture (cont.) Advantages: the instruction cache improves the performance of the Harvard architecture. I/O controller connected to data memory this dedicated hardware allows the data streams to be transferred directly into memory without having to pass through the CPU's registers. Disadvantages: If we were executing random instructions, this situation would be no better at all. 9/20/2018

Architecture of the DSP(Cont.) Now let's look inside the CPU 9/20/2018

Architecture of the DSP(Cont.) At the top of the diagram are two blocks labeled Data Address Generator (DAG), one for each of the two memories. These control the addresses sent to the program and data memories, specifying where the information is to be read from or written to. 9/20/2018

Architecture of the DSP(Cont.) The data register section : contains16 general purpose registers of 40 bits each. These can hold intermediate calculations, prepare data for the math processor, serve as a buffer for data transfer, hold flags for program control. 9/20/2018

Architecture of the DSP(Cont.) The math processing is broken into three sections, a multiplier (MAC), an arithmetic logic unit (ALU), and a shifter. 9/20/2018

Outlines DSP processors Architecture Data handling Program flow Programming Applications

Data handling DSP processors fall into two major categories based on the way they represent numerical values and implement numerical operations internally. Floating Point Fixed Point 9/20/2018

Data handling (Cont.) Floating point Floating point processors primarily represent numbers in floating point format. Advantages: Easier to develop code.. The large dynamic range available means that dynamic range limitations can be practically ignored in a design. Disadvantages: More expensive because they implement more functionality (complexity )in silicon and have wider buses (32 bit). 9/20/2018

Data handling (Cont.) Fixed point Fixed point processors represent and manipulate numbers as integers. Advantages: lower cost and higher speed Disadvantages: Added design effort for algorithm implementation analysis, and data and Coefficient scaling to avoid accumulator overflow (16-20-24 bit). 9/20/2018

Data handling (Cont.) FIR filters (Finite Impulse Response) Let’s take an example: FIR filters (Finite Impulse Response) y[n]=b0 x[n] + b1 x[n-1] + b2 x[n-2] + ……. + bN x[n-N] Structurally, FIR filters consist of just two things: a sample delay line and a set of coefficients. Round Or Truncate (at fixed point) 9/20/2018

Outlines DSP processors Architecture Data handling Program flow Programming Applications

Program flow Pipelined Hardware-controlled looping 9/20/2018

Program flow Pipelined Hardware-controlled looping 9/20/2018

Pipelined Fetch Decode Execute A pipeline is a set of data processing elements connected in series, so that the output of one element is the input of the next one. Instruction pipelines, used in processors to allow overlapping execution of multiple instructions. 1st CLK Cycle 2nd CLK Cycle 3rd CLK Cycle Fetch Fetch ‘A’ Fetch ‘B’ Fetch ‘C’ Decode ‘A’ Decode Decode ‘B’ Execute Execute ‘A’ 9/20/2018

Pipelined (cont.) 1st Approach Each clock cycle = 20ns One instruction = 80 ns each stage of instruction execution is idle 75 % of the time. 9/20/2018

Pipelined (cont.) 2nd Approach One instruction is now completed every clock cycle (every 20 ns) 9/20/2018

Program flow Pipelined Hardware-controlled looping 9/20/2018

Hardware-controlled looping DSP algorithms frequently involve the repetitive execution of a small number of instructions (ex: FIR and IIR filters, FFTs and matrix multiplication) DSP processors have evolved to include features to efficiently handle this sort of repeated execution. MOV #16,B LOOP : MAC (R0)+,(R4+),A DEC B JNE LOOP RPT #16 MAC (R0)+,(R4+),A 9/20/2018

Outlines DSP processors Architecture Data handling Program flow Programming Applications

Programming Most DSPs are programmed in special versions of C. DSP vendors will almost always provide support for C++ programming, but it is not very popular in the DSP software industry. Some DSP software programmers will resort to assembly programming for DSPs.  9/20/2018

Outlines DSP processors Architecture Data handling Program flow Programming Applications

Applications Digital cameras. Digital radios. High-resolution printers. Satellites. 9/20/2018

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