5x5 Pixel Array Status 3 Dec 2003

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Presentation transcript:

5x5 Pixel Array Status 3 Dec 2003 Sam Burke Sean Stromberg UCSB HEP Group UCSB ASIC BiWeekly Status Meeting

ASIC Progress AMI CMOS 0.35 Design Kit 2 Received Design Manual C035MD Ver 5 Design Manual C035MA Ver 3 Core Cells, D Scan FF’s, LVDS Library Pad Limited and Core Limited I/O Cells Ver 1.8 Databook, Ver1.0 Technology Info UCSB ASIC BiWeekly Status Meeting

Tri-State Inverter The 3state Inverter will be the building block for the D FlipFlops Inverter Td=1.6 ns h/l Td=3.9 ns l/h Gated Td=1.5 ns h/l Td=1.2 ns l/h See web page for details UCSB ASIC BiWeekly Status Meeting

DFFR D Flip Flop with Reset 4 inverters 3 tri-state inverters 1ea 2 input NOR 1ea 2 input tri-state NOR 30 separate FET’s in design! UCSB ASIC BiWeekly Status Meeting

UCSB ASIC BiWeekly Status Meeting

Future Plans Adjust switching point of standard inverter 50% Vcc Simulate Ring Oscillator to determine propigation delays using standard approach. Simulate D Flip Flop with Reset and Compare with standard? Investigate other topologies with fewer FET’s. UCSB ASIC BiWeekly Status Meeting