IP – Based Design Methodology Daniel D. Gajski University of California gajski@uci.edu http://www.ics.uci.edu/~gajski

Outline Drivers of IP business Obstacles to IP success Possible solutions Business models Future

IP Drivers Product complexity Market pressure Expertise shortage Productivity gap Business model

Solving Complexity / Productivity Problems IP 1. IP 2. 3. IP 4. IP

Obstacles to IP Success Partially abstracted design process Simulation based design flow Simulation models are not easily synthesizable IP definition (parameterization, verification, characterization) IP-centric models for SOC No separation of computation and communication Need for encapsulation Reuse automation IP do not fit into past methodologies and tools IP-centric methodology No clearly defined business models Volume, value-added and protection

Solving Complexity / Productivity Problems Higher level of abstraction Specification Architecture Communications Components (IP) Tools and methodologies Standardization Languages Models Protocols Documentation (IP)

Simulation Based Design Flow Simulatable but not synthesizable 3.415 2.715 case X is when X1 => when X2 => Finite State Machine Table Lookup Controller Memory

IP Definition Quality, verification, characterization vs. parameterization Quality, Verifiability, Testability, Characterizability 1 single instance No. of parameters, Generality

RTL Specs FSM FSMD S1 S1 S2 S2 S3 S3 x = 0 y = 0 ... count = n x = 0 temp1 = a(i) + b(i) temp2 = c(i) + d(i) count = count - 1 S2 S2 Count ¹ 0 Count ¹ 0 x = 1 y = 0 ... S3 S3 s(i) = temp1 * temp2 Count = 0 Count = 0 FSM FSMD

Processor (controller & datapath) RTL Architectures Inputs Control Data Count D Q FF State reg. or PC Mem Mem RF RF RF . . . Outputs D Q FF +/- + temp1 temp2 Input logic State reg. Ouput logic Controller Datapath Control Data Controller Processor (controller & datapath)

variable A: array[1..20] of integer IP-centric Specs S1 Y variable A: array[1..20] of integer C Program ………….. A D B variable i, max: integer; max = 0; for i = 1 to 20 do if (A[i] > max) then max = A[i]; end if; end for; S2 e1 e2 C S3 e3 SFSMD Concurrent, hierarchical SFSMD

IP-centric Architecture Control Processor SR/PC Mem RF RF IP Processor IP IP IP IP IP Ctrl DP Ctrl DP temp1 temp2 Controller Datapath IP-centric processor IP-centric system

IP-Centric Models Present IP Future B T C W IP

Reuse Explorations Behavior IP Channel IP synthesizable behavior PE replicable T IP at any time synthesizable behavior wrapped IP behavior transducer Channel IP at any time virtual channel channel with IP protocol C IP replicable

Reuse Optimization Wrapper Resolution (a) Two synthesizable behaviors connected by a channel A B A B C (b) Synthesizable behavior connected to an IP A A W IP IP (c) IP connected through an incompatible channel A T C W IP B T A T IP

CAD Methodology Capture – Simulate (60’s – 80’s) Describe – Synthesize (80’s – 00’s) Specify-Explore-Refine (00’s – 20’s)

Past, Present and Future Capture & Simulate Describe & Synthesize Specify, Explore & Refine Executable Spec Functionality Specs Specs Algorithms Algorithms (software) Algorithms Connectivity Architecture Protocols Communications Describe Design Design Design Timing Logic Simulate Logic Logic Simulate Physical Physical Physical Manufacturing Manufacturing Manufacturing

Present and Future Issues Describe & Synthesize Specify, Explore & Refine Manufacturing Describe Simulate Specs Algorithms (software) Physical Logic Design Executable Spec Functionality Issues: IP vs EDA Semi’ vs. Systems Simulation vs. Synthesis Hardware vs. Software VHDL vs. C Top-down vs. Bottom-up Integrated vs. Outsourced CE vs. CS Algorithms Connectivity Architecture Protocols Communications Design Timing Logic Physical Manufacturing

Analysis and validation flow SpecC Methodology Specification model IP SW synthesis HW Manufacturing Validation of algorithm and functionality Estimation Simulation Communication Architecture Implementation functionality and synchronization communication timing and performance Synthesis flow Analysis and validation flow Architecture exploration

Business Model Product, Knowledge System house IP EDA Providers vendors Design house Integrators Commodity IPs, Standard IPs, Star IPs Tools, Libraries Manufacturing Technology, Libraries

Scenario 1: Design world Business Model Product, Knowledge System house IP providers EDA vendors Design house Integrators Tools, Libraries, Commodity IPs, Standard IPs Star IPs Manufacturing Technology Scenario 1: Design world

Scenario 2: Split Design Business Model Product, Knowledge System house Design house IP providers EDA vendors Integrators Tools Star IPs Manufacturing Technology, Libraries, Commodity IPs, Standard IPs Scenario 2: Split Design

Scenario 3: IP Providers World Business Model Product, Knowledge, Assembly System house IP Providers EDA vendors Standard IPs, Star IPs, Commodity IPs Tools, Libraries Manufacturing Technology, Libraries Scenario 3: IP Providers World

Scenario 4: Systems world Business Model Product, Knowledge System house IP providers EDA vendors Tools, Libraries, Commodity IPs, Standard IPs Star IPs Manufacturing Technology Scenario 4: Systems world

Top-down vs. Bottom-up Spec Spec Real Comp. (hard) Virtual Comp. (soft) Layout Layout Manuf. Manuf.

Reuse Paradigm New Languages, guidelines, extensions Models for exploration (spec, arch, comm, RTL) Separation of computation & communication Encapsulation IP automation standards Reuse automation (Synthesis with reuse) IP-centric methodology

Conclusion