Entegra’s SDR Module Dual 14 bit 65Msps A/D converters with a sampling bandwidth of 200MHz. Dual 14 bit 100Msps D/A converters. 2 million equivalent gate Xilinx V2000E FPGA On-board RAM: 1MB Sync Burst SRAM, 128kB dual-port SRAM. On-board high stability 10MHz reference and programmable DDS to support virtually any clock scheme currently in use. 24/48 bit high speed LVDS or LV-TTL digital interface 2MB FLASH ROM for FPGA configuration, also configurable via JTAG or DSP bus. Omnibus DSP interface compatible with a range of Innovative Integration DSP cards. Compact: 100mm x 160mm mezzanine mounting module. Today's wireless industry is founded on many different radio systems and agreed standards used in many different applications. Our position as a wireless system consultancy business producing turn-key solutions has required the development of our own Software-Defined Radio (SDR) module. This module used in combination with our existing range of TI C6x DSP-based products provides a flexible solution to many wireless applications ranging from simple RF signal generation and capture through to advanced 3G air-interface applications.

W-CDMA Downlink Simulator test-bed for experimenting with system partitioning in a user terminal he simulator is based on a Software Defined Radio (SDR) module and a TMS320C6201 DSP card. The FPGA is the physical channel processor providing most of the functions required to implement an FDD downlink. It has an 8-channel basestation (Node-B) emulator, a 12 finger rake receiver, searcher matched filter and a digital radio transceiver function. The C6x DSP supports the physical channel processor configuring channels, handling buffer and timing interrupt control and streaming data to and from the FPGA. It also runs the customer's algorithms and can be linked to a PC host (via PCI bus) and additional DSP cards using a high speed FIFO buffer.

Internal architecture of the physical channel processor FPGA hilst there are many digital down-converter ICs available on the market, the advantage of using the FPGA for digital frequency conversion is complete design flexibility. Some applications may require higher numerical precision, greater Spur-Free Dynamic Range (SFDR) or more sophisticated filtering than any COTS IC solution can offer. The interface to the RF section is provided by low-noise I and Q channels which are nominally driven at 0dBm into 50W. Optional 7th order elliptic filters are available on the SDR module to provide low-pass channel filtering. The user can fit components to change the filter characteristics or bypass them altogether. An optional dithering circuit can be connected to the A/D converter inputs to improve the SFDR of the AD6644 A/D converters. The input can be either in complex I+jQ form (such as that from the 2nd IF of a typical receiver RF section) or at an IF up to 200MHz which is under-sampled by the A/D converter. Alternatively, the digital I/O port can be used to interface to A/D and D/A converters on a different module or to a serializer chip. The digital section of the transceiver consists of a complex digital down-converter (DDC) and Digital Up-Converter (DUC). Both have their own Numerically Controlled Oscillators (NCO) which have an SFDR of >100dB. Since the A/D converters can have up to 100dB SFDR, it is important that the spectral purity of the input signal is maintained hence the stringent requirement of the NCO SFDR. In order to obtain this sort of performance from the NCO, an interpolation technique has been applied which provides about 30dB more SFDR performance compared to a conventional NCO with dithering alone. The NCO can be tuned from -30MHz to +30MHz in 0.01Hz steps. It can be used to remove any carrier frequency offset converting the signal to an exact 0Hz IF.

The digital down-converter and filters the ADC and DAC sample rate is 61.44MHz, 16x the chip rate of 3.84MHz. The output from the DDC is decimated by 4 down to 15.36MHz prior to further filtering. The down-converter is equipped with a fully programmable 64 tap FIR filter with 14 bit coefficients. This filter defaults to providing a Root-Raised Cosine response with a roll-off factor (a) of 0.22. However, any set of sixty-four symmetrical coefficients can be loaded whilst the filter is operating. This enables the filter to be used as part of an adaptive filter algorithm. Following the channel filter is an AGC gain control. The rake receiver has a numerical precision of 4-bits. The AGC is used to compress the potentially large dynamic range of the input signal down to 24dB for the rake receiver. The rake receiver's numerical precision can be changed relatively easily by the use of constants defined in a VHDL package. The down-converter is equipped with a 2048 word I/Q FIFO buffer which can be switched between the DDC output, the decimation filter, pulse shaping filter or AGC. The buffer is useful for capturing the received signal for analysis. EnTegra has created a vector signal analysis application using this buffer to capture the signal. A host PC displays the signal in time, frequency and X/Y forms and to measure W-CDMA Adjacent Channel Leakage Ratio (ACLR). In the downlink emulator application, the DSP uses the buffer to capture the signal for AGC setting purposes.

Digital Up-Converter (DUC) Digital Up-Converter (DUC) converts baseband, chip-rate symbols to a filtered and over-sampled form either in I+jQ or IF format. In many respects it is the reverse process of the digital down-conversion. The input to the DUC can be either from a 2048 word FIFO buffer or from the 8-channel W-CDMA modulator. The output from either the buffer or the modulator is at chip-rate (3.84MHz). A 128-tap fully programmable polyphase FIR filter is used to perform Root-Raised Cosine (RRC) pulse shaping and interpolation up to a sample rate of 8x chip-rate. This filter may be bypassed if required. The final interpolation from 8x to 16x chip-rate is accomplished by a half-band IIR filter. The 16x over-sampled signal is then modulated onto a carrier using a complex multiplier and NCO very similar to that used in the digital down-converter. The NCO may be set between -30MHz and +30MHz in 0.01Hz steps thus offsetting the carrier from 0Hz. A final stage of DC-offset correction is applied to compensate for any DC offsets in the down-stream analogue sections. The output from the AD9764 D/A converters is at 16x chip-rate. The measured ACLR is typically >50dB. A digital loop-back mode is available whereby the output from the DUC is connected to the input of the DDC. This is particularly useful for testing algorithms where a perfect link is required to enable other parameters to be adjusted without interference.

Rake Receiver The Rake receiver uses a combination of hardware and DSP software for maximum flexibility to enable a range of alternative receiver algorithms to be investigated in DSP. The hardware provides twelve rake fingers divided into six master-slave pairs. The master finger incorporates a Delay Locked Loop (DLL) which tracks early and late code phases (1/2 chip apart in time) . Normally the master finger is used to receive the common pilot channel (CPICH). The DLL tracks a multi-path signal which may have varying degrees of Doppler shift present (ie the time delay is changing as the source moves relative to the receiver or vice versa). The chip-rate clock which controls the scrambling code generation is tuned to track the varying time delay. The slave finger shares the same scrambling code and timing as the master finger but can have a different spreading code assigned to it. It is normally used to receive the data channel. Its chip-timing follows that of the master finger's DLL but its associated output buffer can be turned on and off under control of the counter timing control logic. The spreading factors of master and slave can be independently set between 2 and 256. Each master-slave rake finger pair thus has two de-spreaders and two complex outputs feeding double buffers whose length is programmable between 0 and 128 words. Each 32-bit word represents two complex symbols (ie two I/Q pairs) each of 8 bits resolution. The Maximum Ratio Combining (MRC) is performed by the DSP. The DSP physical channel resource manager software assigns rake fingers to receive channels; a receive channel can have one or more fingers allocated to it. Each receive channel is assigned an MRC summing buffer into which its rake finger outputs are combined. For each rake finger, the complex signal from the slave channel is conjugate-multiplied with the tap-weight which is estimated as a running average of the pilot signal from the master finger. The weighted signals are then summed in the MRC buffer prior to symbol detection. AGC Ancillary functions such as AGC are performed by the DSP. The AGC is estimated on a slot-by-slot basis by using the receive signal FIFO in a timed mode to capture a burst of receiver input signal in each slot. The mean signal power is calculated from the burst and the AGC gain control set according to a log2 conversion. The wide-band signal power is also calculated.

Searcher Receiver Matched Filter The searcher receiver is used to profile the propagation channel between the transmitter and receiver. The peaks in the resulting power-delay profile can then be used to control the positioning of rake fingers in terms of timing. The Primary Synchronisation Channel (P-SCH) transmitted by all UTRAN Node-B's is detected using a 1024 tap matched filter sampling at 4x chip-rate. Arguably, ¼ chip timing resolution is far more than is required for a DLL-based rake receiver since the rake fingers can be positioned within 1 chip of the ideal timing position and will nearly always lock on to the signal. However, for experimentation with indoor propagation models, a high resolution filter was demanded. The matched filter can be activated either "on-demand" or regularly under hardware timer control at a specified quarter-chip timing offset within each slot. Either way, the DSP uses the results of the matched filter to estimate the channel's time delay. In the case of multiple propagation paths, the DSP can allocate rake fingers to different paths, usually no more than four fingers for each channel. The P-SCH matched filter can also be used for identifying adjacent cells and measuring their relative power for handover purposes because the same P-SCH code sequence is transmitted across all cells.

Eight Channel W-CDMA Transmitter Each of the eight transmit channels has a 128 x 32-bit word double-buffer. The DSP writes pairs of QPSK symbols to the buffer as four data bits together with 28 bits of I/Q gain information. Thus each symbol represented by an I/Q pair is represented by 8 bits of I gain and 8 bits of Q gain. Whilst this represents a very large overhead in terms of bits per symbol, the advantage is that both the gain and phase of each channel can be changed on a symbol-by-symbol basis. This enables the experimental system to generate virtually any type of W-CDMA modulation including DTX, power control, AICH channels (which use M-ary modulation) and closed-loop transmit diversity. The power can be varied over a 0 to -20dB range and the phase over 0-2p. Each channel has a spreading code generator (spreading factors between 2 and 256) and a scrambling code generator. Whilst each channel can be assigned its own spreading code and scrambling code, the timing of the scrambling code generators are locked to the cell's frame timing. All scrambling code generators have the same phase in terms of the 38400 chipping sequence length which repeats every 10ms radio frame. Combined with the eight general purpose channels are two dedicated channels; Primary SCH (P-SCH) and Secondary SCH (S-SCH). These channels are dedicated though their gain and phase can be independently changed. The S-SCH channel transmits a sequence of fifteen Hadamard codes in a 15-slot frame. The sequence of code numbers depends upon the selected scrambling code group. This is programmed by the DSP.

Timing Controller The timing control logic is responsible for enabling and disabling the various parts of the receiver and transmitter in relation to a time-base. For instance, a transmit channel can be turned on at chip 300 in slot 0 and turned off at chip 70 in slot 15. Similarly the master and slave rake fingers can be enabled and disabled at different timing offsets. The FIFO buffers and SCH matched filter are also controlled by the timing logic. The timebase for the whole system is a quarter-chip resolution counter called the Slot Timing Counter (STC). It counts from 0 to 10239 in each slot. The slots are counted by the Frame Timing Counter (FTC), 0-14. The FTC controls the scrambling code re-loading for each transmitter's scrambling code generator, forcing a re-load of the shift-registers at chip 38399 (last chip of slot 14). The timebase thus establishes the transmit cell timing. The receiver timing can be offset from the transmit timing using a Slot Interrupt Timing Register (SITR). The DSP is interrupted at the slot rate (1500Hz). Slot-level tasks such as AGC are scheduled at this rate. The DSP is also interrupted by the FIFO buffers in the rake receiver and transmitter. In total there are thirty interrupt sources most of which originate from the FIFO buffers. The DSP services the transmit buffer interrupts by writing fresh QPSK symbols to be spread and modulated. It services the receive buffer interrupts by emptying the contents and performing maximum ratio combining. The master finger outputs are averaged to calculate tap weights.

DSP Software Structure he C6x DSP software is written in 'C' and is arranged in layers as shown above. The DSP communicates with the FPGA hardware using a library of hardware drivers. The physical layer tasks such as interrupts and low-level algorithms such as AGC and timing adjustments are executed by the slot and buffer interrupt threads using a number of Physical layer (L1) support functions. The higher levels of the physical layer software such as physical channel implementations gain access to the physical layer resources by means of Resource Management Functions. These functions provide a view of the transmit and receive channels as a resource which is allocated in a similar manner to a resource such as memory. For instance, when the application needs a receive channel it calls an alloc_rx_channel() function specifying the channel rate, scrambling code, spreading code, number of rake fingers and buffer sizes. The function then returns a handle which must be used to access the allocated resource via other functions. The transmit channels are allocated in a similar manner and resources may be freed up after use by calling a free_rx_channel() function for example. The physical layer offers its services to the L1 application code and to another processor using a host Application Programming Interface (API). EnTegra's host API offers a range of functions including high speed data streaming (eg for multi-media 3G applications) and real-time DSP debugging. Using the host API, a whole range of applications can be written with a common interface to the underlying physical layer.