The Processor and Machine Language Computer Science 101 The Processor and Machine Language

The Processor The control unit Sequences and executes the instructions The ALU Performs primitive arithmetic and logic Registers High-speed memory cells that serve special functions for the two units

The ALU in Action a b a + b a - b a * b a / b One circuit for each function, all performing simultaneously

The ALU in Action a b a + b a - b Output Multiplexor circuit a * b line 0 a + b line 1 a - b Output Multiplexor circuit a * b line 2 a / b line 3 Selector lines 00, 01, 10, 11 are codes that determine which input is sent out

Executing Instructions Program instructions, written in machine language, are stored in memory The control unit Fetches an instruction from memory Decodes the instruction Executes the instruction Repeats this until a halt instruction is reached

Format of a Machine Language Instruction Let’s assume a memory cell size of 16 bits and an address space of 12 bits. Then, each instruction consists of a 4-bit opcode a 12-bit operand code, called the address field 1 1 1 1 1 1 1 1 1 1 opcode address field

Interpreting an Instruction The opcode 1101 means input a number and store it in the memory cell specified by the instruction’s address field. So, this particular instruction says, input a number and store it in the cell whose location is 127. 1 1 1 1 1 1 1 1 1 1 opcode address field

Registers We’ve already seen the memory data register (MDR) and the memory address register (MAR), which are used for fetching and storing data. MDR 1 1 1 1 1 1 1 1 1 1 MAR 1 1 1 1 1 1

Other Registers Program counter (PC) 12 bits Contains the address of the next instruction Instruction register (IR) 16 bits Contains the currently executing instruction Data register (R) 16 bits Used for temporary storage by some instructions Condition code register (CCR) 3 bits Used to test data and make decisions

Other Registers PC 1 1 1 1 1 1 IR 1 1 1 1 1 1 1 1 1 1 R 1 1 1 1 1 1 1 1 1 1 CCR 1 The state of the program at any given time is determined by the data contained in memory (RAM) the registers

The Instruction Set We will want instructions for Input and output Moving data from RAM to the data register and back again (like assignment statements) Arithmetic (at least addition and subtraction) Making decisions based on comparisons of two data values (if statements and loops)

The Instruction Set A machine’s instruction set depends on the number of possible opcodes 4 bits allows 24 or 16 possible opcodes In general, N opcodes requires log2N bits

The 16 Opcodes and Their Operations Binary opcode Operation 0000 LOAD X 0001 STORE X 0010 CLEAR X 0011 ADD X 0100 INCREMENT X 0101 SUBTRACT X 0110 DECREMENT X 0111 COMPARE X 1000 JUMP X 1001 JUMPGT X 1010 JUMPEQ X 1011 JUMPLT X 1100 JUMPNEQ X 1101 IN X 1110 OUT X 1111 HALT X = a memory address

Data Movement – 0000 (LOAD) LOAD X Copy the contents of the cell at address X into the data register R LOAD X = 000000001101 IR 1 1 1 R 1 1 1 1 1 1 1 1 1 1 RAM 000000001101 1 1 1 1 1 1 1 1 1 1

Data Movement – 0001 (STORE) STORE X Copy the contents of the data register R into the cell at address X STORE X = 000000001101 IR 1 1 1 1 R 1 1 1 1 1 1 1 1 1 1 RAM 000000001101 1 1 1 1 1 1 1 1 1 1

Arithmetic – 0011 (ADD) ADD X Add the contents of the data register R to the contents of the cell at address X and leave the sum in the data register R ADD X = 000000001101 IR 1 1 1 1 1 2 + 3 R 1 RAM 000000001101 1 1

Arithmetic – 0011 (ADD) Add the contents of the data register R to the contents of the cell at address X and leave the sum in the data register R ADD X = 000000001101 IR 1 1 1 1 1 2 + 3 = 5 R 1 1 RAM 000000001101 1 1

General Method for Addition (Z = X + Y) LOAD the value at address X ADD the value at address Y STORE into address Z

Example: Set Z to X + Y Fetch instruction at address stored in PC (0) IR R RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example: Set Z to X + Y Increment PC PC IR 1 1 R RAM 000000000000 1 1 IR 1 1 R RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y Execute the instruction in IR PC 1 IR 1 1 R 1 IR 1 1 R RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y Fetch the next instruction PC 1 IR 1 1 R 1 1 IR 1 1 R 1 RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y Increment the PC PC 1 IR 1 1 1 R 1 RAM 1 IR 1 1 1 R 1 RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y Execute the instruction in IR PC 1 IR 1 1 1 R 1 IR 1 1 1 R 1 RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y Fetch the next instruction PC 1 IR 1 1 1 R 1 1 IR 1 1 1 R 1 1 RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y Increment the PC PC 1 IR 1 1 1 R 1 1 RAM 1 IR 1 1 1 R 1 1 RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y Execute the instruction in IR PC 1 1 IR 1 1 1 1 1 IR 1 1 1 R 1 1 RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101

Example : Set Z to X + Y PC 1 1 IR 1 1 1 R 1 1 RAM 000000000000 1 1 1 1 IR 1 1 1 R 1 1 RAM 000000000000 1 1 000000000001 1 1 1 instructions 000000000010 1 1 1 x 000000000011 1 y 000000000100 1 1 data z 000000000101 1 1