VLSI Testing http://www. engr. uconn. edu/~tehrani/teaching/test/index 21 September 2018

Objective Need to understand Types of tests performed at different stages Verification Testing Manufacturing Testing Acceptance testing Automatic Test Equipment (ATE) technology Influences what tests are possible Measurement limitations Impact on cost Parametric test 21 September 2018

Types of Testing Testing principle Apply inputs and compare “outputs” with the “expected outputs” Verification testing, or design debug Verifies correctness of design and of test procedure usually requires correction to design Characterization testing Used to characterize devices and performed through production life to improve the process Manufacturing testing Factory testing of all manufactured chips for parametric faults and for random defects Acceptance testing (incoming inspection) User (customer) tests purchased parts to ensure quality 21 September 2018

Testing Principle 21 September 2018

Verification Testing Ferociously expensive Often a software approach But, may comprise: Scanning Electron Microscope tests Bright-Lite detection of defects Electron beam testing Artificial intelligence (expert system) methods Repeated functional tests 21 September 2018

Manufacturing Test (Also called production test) Determines if manufactured chip meets specs Must cover high % of modeled faults Must minimize test time (to control cost) No fault diagnosis Tests every device on chip Tests are functional or at speed of application or speed guaranteed by supplier 21 September 2018

Burn-in or Stress Test Process: Catches: Subject chips to high temperature & over-voltage supply, while running production tests Catches: Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers Freak failures – devices having same failure mechanisms as reliable devices 21 September 2018

Sub-types of Tests Parametric Tests: Functional Tests: measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap. Functional Tests: used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive. the focus of this ECE 300 and today’s lecture 21 September 2018

Two Different Meanings of Functional Test ATE and Manufacturing World any vectors applied to cover high % of faults during manufacturing test Automatic Test-Pattern Generation World testing with verification vectors or vectors generated without structural information, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %) 21 September 2018

Automatic Test Equipment (ATE) ADVANTEST Model T6682 ATE 21 September 2018

T6682 ATE Block Diagram 21 September 2018

T6682 ATE Specifications Uses 0.35 mm VLSI chips in implementation 1024 pin channels Speed: 250, 500, or 1000 MHz Timing accuracy: +/- 200 ps Drive voltage: -2.5 to 6 V Clock/strobe accuracy: +/- 870 ps Clock settling resolution: 31.25 ps Pattern multiplexing: write 2 patterns in one ATE cycle 21 September 2018

Electrical Parametric Testing Typical tests: DC parametric test Probe test (wafer sort) – catches gross defects Contact, power, open, short tests Functional & layout-related test AC parametric test Unacceptable voltage/current/delay at pin Unacceptable device operation limits 21 September 2018

Economics of Design for Testability (DFT) Consider life-cycle cost; DFT on chip may impact the costs at board and system levels. Weigh costs against benefits Cost examples: reduced yield due to area overhead, yield loss due to non-functional tests Benefit examples: Reduced ATE cost due to self-test, inexpensive alternatives to burn-in test, improved fault coverage 21 September 2018

Benefits and Costs of DFT Design and test + / - Fabri- cation + Manuf. Test - Level Chips Boards System Maintenance test Diagnosis and repair Service interruption + Cost increase - Cost saving +/- Cost increase may balance cost reduction 21 September 2018

VLSI Chip Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip: Cost of fabricating and testing a wafer -------------------------------------------------------------------- Yield x Number of chip sites on the wafer 21 September 2018

Clustered defects (VLSI) VLSI Defects Good chips Faulty chips Defects Wafer Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77 21 September 2018

Fault Modeling Models are often easier to work with Models are portable Models can be used for simulation, thus avoiding expensive hardware/actual circuit implementation Nearly all engineering systems are studied using models All the above apply for logic as well as for fault modeling Be sure everyone has a conduct sheet. Re GROUND RULES: 1. In terms of allowed collaboration vs. individual work, ask if you are not sure. 2. Deactivate all cell phones or pagers during class unless you are on-call during your job. 3. No tape-recording permitted. Take notes. 21 September 2018

Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments 21 September 2018

Some Real Defects in Chips Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) Time-dependent failures (Age defects) Dielectric breakdown Electromigration Packaging failures Contact degradation Seal leaks Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. 21 September 2018

Defect, Fault, and Error Defect (imperfection in hardware): Error: A defect in an electronic system is the unintended difference between the implemented hardware and its intended design. Error: A wrong output signal produced by a defective system is called an error. An error is an “effect” whose cause is some “defect”. Fault (imperfection in function): A representation of a “defect” at the abstracted function level is called a fault. 21 September 2018

Occurrence frequency (%) Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 8 5 Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. 21 September 2018

Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults 21 September 2018

Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value c j 0(1) s-a-0 a d 1(0) g 1 h z i 1 b e 1 k f Test vector for h s-a-0 fault 21 September 2018

Single Stuck-at Faults (contd.) How effective is this model? Empirical evidence supports the use of this model Has been found to be effective to detect other types of faults Relates to yield modeling Simple to use Show a slide on overhead 21 September 2018

Why Not Multiple Stuck-at Faults In general, several stuck-at faults can be simultaneously present in the circuit. A circuit with n lines can have 3n-1 possible stuck line combinations. There are three states: s-a-1, s-a-0, and fault-free Even a moderate value n will give an enormously large number of multiple stuck-at faults. It’s a common practice to model only single stuck-at faults. A n-line circuit can have at most 2n single stuck-at faults. This number is further reduced by techniques known as Fault Collapsing. Show a slide on overhead 21 September 2018

Checkpoints Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10 21 September 2018

Fault Simulator in a VLSI Design Process Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled fault list Remove tested faults Test compactor Delete vectors Fault coverage ? Low Test generator Add vectors Adequate Stop 21 September 2018

Example HA HA1 HA2 a b c d e f Half-Adder A B C D E F Sum Carry Full-Adder 21 September 2018

Example FA0 FA1 FA2 FA3 C0 S0 A0 B0 C1 S1 A1 B1 C2 S2 A2 B2 C3 S3 A3 21 September 2018

Fault Simulation Results 4-bit FA: 36 logic gates, 9 PIs, 5POs, 186 single stuck-at faults. Vector Number 186 Uncollapsed Faults 114 Collapsed Faults Detected Coverage 1 2 3 4 5 6 61 113 125 143 162 186 33% 61% 67% 77% 87% 100% 37 65 77 89 102 114 32% 57% 68% 78% 89% 7 8 21 September 2018

Fault Simulation Algorithms Serial Parallel Deductive Concurrent Others Differential Parallel pattern etc. 21 September 2018

Combinational ATPG Structural vs. functional test Definitions Completeness Conditions for finding a test Algebras Types of Algorithms – classical Complexity Do not discuss much about topics here. Under computer system overall implies what is a compute system - its architecture and components Then focus on hardware and software components 21 September 2018

Functional vs. Structural ATPG 64-bit ripple-carry adder 21 September 2018

Carry Circuit 21 September 2018

Functional vs. Structural (Contd.) Functional ATPG – generate complete set of tests for circuit input-output combinations 129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ % 21 September 2018

History of Algorithm Speedups D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) 1 7 23 292 1574 ATPG System 2189 ATPG System 8765 ATPG System 3005 ATPG System 485 25057 Year 1966 1981 1983 1987 1988 1990 1991 1993 1995 1997 21 September 2018

Fault Coverage and Efficiency # of detected faults Total # faults Fault coverage = Fault efficiency # of detected faults Total # faults -- # undetectable faults = 21 September 2018

ATPG Systems Circuit Description Fault List Compacter Test generator With fault simulation Aborted Faults Test Patterns Backtrack Distribution Undetected Faults Redundant Faults 21 September 2018

Sequential Circuit ATPG A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Be sure everyone has a conduct sheet. Re GROUND RULES: 1. In terms of allowed collaboration vs. individual work, ask if you are not sure. 2. Deactivate all cell phones or pagers during class unless you are on-call during your job. 3. No tape-recording permitted. Take notes. 21 September 2018

Methods Methods Time-frame expansion methods Simulation-based methods Forward time, reverse time, forward and reverse time Simulation-based methods 21 September 2018