Processor Pipelining Yasser Mohammad

What is pipelining

MIPS PIPELINE Instruction Fetch Instruction Decode/Register Read Execution/ Address Calculation Memory Access Writeback

Why is pipelining useful? The key is maximal utilization of the pipeline. In ideal situations:

MIPS IS is designed for pipelining All instructions the same length (x86 has 1-15bytes instructions) If not so: stalling may be needed between fetching and decoding Few instruction formats (3) with fixed locations of most opcode fields If not so: cannot read registers until we know which instruction is it  6-stages Memory access in load and store only If not so: cannot combine address calculation and execution  7 stages Operand alignment If not so: 2 stages may be needed to transfer data  8 stages All Instructions write at most one result If not so: forwarding cannot be used (more on that later)

Pipeline hazards Structural Hazards Data Hazards Control Hazards Example: single memory in MIPS Solution  Good IS design More problematic in FP units Data Hazards Example: Solution: Forwarding + programmer’s awareness + translator’s support Both integer and FP units Control Hazards Example any branch Solution: stall on branch | branch prediction | delayed branch

Data hazards and forwarding

Data hazards and instruction reordering