D Flip-Flop

Lecture Overview D Flip-Flops Logic Synchronization Types of D Flip Flops Sample Flip-Flop Applications

Positive Edge Triggered D Flip-Flop CLK  Q n+1 1 D Positive Edge Triggered D Q Q CLK D Q

Logic Synchronizing Data enters here at different times Example: Parallel Port Data enters here at different times Data goes out at the same time on a clock pulse

Types of D Flip-Flops D Q Q Positive Edge Triggered Negative Edge Triggered D Q Q

Types of D Flip-Flops D Q Q Positive Level Triggered D Q Q Negative Level Triggered

Asynchronous Inputs D Q Q D Flip-Flop w/ Preset D Q Q P-SET D Flip-Flop w/ Clear D Q Q CLR

Asynchronous Inputs D Flip-Flop w/ Preset & Clear D Q Q P-SET CLR

D Flip-Flop w/ Preset & Clear Q n+1 1 (preset) 0 (clear) ? (illegal) 1 CLK X  D CLR P-SET D Q Q P-SET CLR

Application of D Flip-Flops Data Storage Counters & State Machine Designs Logic Synchronizing Divide By Circuits

Divide By Circuit with D Flip-Flop

Divide By Circuit - Simulation