Assistant Prof. Fareena Saqib Florida Institute of Technology ECE - 1551 Digital logic Lecture 18: Synchronous Sequential Logic Contd Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 11/10/2015

Recap Sequential Logic: Latches and Flip Flops 2018/9/21 Recap Sequential Logic: Output depends not only on current input but also on past input values, e.g., design a counter Need some type of memory to remember the past input values Latches and Flip Flops SR Latch S’R’ Latch D Latch SR FF D FF JK FF T FF 2018/9/21 Sequential Circuits

Agenda Characteristic Table Excitation Table Finite State Machine

Sequential Circuits Circuits that we Information Storing have learned 2018/9/21 Sequential Circuits Circuits that we have learned so far Information Storing Circuits Timed “States” 2018/9/21 Sequential Circuits

Combinational Circuits Sequential Logic Sequential Logic circuits remember past inputs and past circuit state. Outputs from the system are “fed back” as new inputs With gate delay and wire delay The storage elements are circuits that are capable of storing binary information: memory Most digital systems like handheld devices, cell phones, navigation receivers, digital watches, digital computers, digital traffic light controllers etc. require memory elements to store information. A sequential circuit is specified by a time sequence of inputs, outputs, and internal states Combinational Circuits Inputs Outputs Memory Elements

SR Latch Characteristic Table Characteristics Table describes the operation of Flip Flop. It is also called Function Table Latch is sensitive to input changes ONLY when C=1 When the enable input goes to 1, information from the S or R input is allowed to affect the latch.

D Latch Characteristic Table D latch is designed to eliminate the indeterminate state in SR latch by making sure that inputs S and R are never equal to 1 at the same time

SR Flip Flop – Characteristic Table S R CLK Q Q’ When C=1, master is enabled and stores new data, slave stores old data. When C=0, master’s state passes to enabled slave, master not sensitive to new data (disabled). 0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Store

D – Flip Flop Configuration Table The construction of a D flip-flop with two D latches and an inverter is shown in Fig. The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative edge of the synchronizing or controlling clock (designated as Clk ). D Q (t+1) ------------------- 0 0 1 1

D-FF using 3 SR Latches Another construction of an edge-triggered D flip-flop uses three SR latches as shown in Fig. Two latches respond to the external D (data) and Clk (clock) inputs. The third latch provides the outputs for the flip-flop. when the input clock in the positive-edge- triggered flip-flop makes a positive transition, the value of D is transferred to Q . A negative transition of the clock (i.e., from 1 to 0) does not affect the output, nor is the output affected by changes in D when Clk is in the steady logic-1 level or the logic-0 level. Hence, this type of flip- flop responds to the transition from 0 to 1 and nothing else.

D – Flip Flop with MASTER and SLAVE Configuration

JK Flip Flop Characteristic Table The JK flip-flop is an SRFF with some additional gating logic on the inputs in which the SR=11 (undetermined condition) doesn’t exist J is used for the set and K is used for reset clk J K Qn+1 ---------------------------- 0 X X Qn 1 0 0 Qn 1 0 1 0 1 1 0 1 1 1 1 Qn’

Toggle Flip Flop Characteristic Table Toggle Flip flop is a special case where we connect J and K input together. clk J K Qn+1 ---------------------------- 0 X X Qn 1 0 0 Qn 1 1 1 Qn’

Characteristics Table / Function Table It is used to describe flip flop logical properties of a flip flop by describing its operation in a tabular form. Q(t+1) is the next state and Q(t) is the current state. J K Q (t+1) D Q (t+1) T Q(t+1) ------------------- ------------------- ------------------- 0 0 Q(t) 0 0 0 Q(t) 0 1 0 1 1 1 Q’(t) 1 0 1 1 1 Q’(t)

JK FF and Toggle FF using D-FF D = JQ’+K’Q J = 1 K = 0 D = Q’+Q = 1 J=0 K=1 D =0 J=K=1 D=Q’ J=K=0 D =Q T FF: D = Q xor T T = 1 D = Q’ T=0 D =Q

Characteristics Equation D-FF Characteristic table can be expressed algebraically with a characteristic equation. For the D-FF we have Q(t+1) = D It means that the next state of the output will be equal to value of D in the present state. JK-FF Q(t+1) = J Q’(t) + K’ Q(t)

Characteristics equation for JK Q(t) Q(t+1) 1 Q(t+1) = m1+m4+m5+m6 Q(t+1) = J Q’(t) + K’ Q(t)

Excitation Table The excitation table rearranges the order of characteristic table. Instead of the truth table inputs being the control bit(s) of the flip flop and Q and the output being Q+. The truth table inputs are now Q and Q+, and the "outputs" is the control bit(s) of the flip flop.   Q     Q+     D     1

Excitation Table - DFF The excitation table rearranges the order of characteristic table. Instead of the truth table inputs being the control bit(s) of the flip flop and Q and the output being Q+. The truth table inputs are now Q and Q+, and the "outputs" is the control bit(s) of the flip flop.   Q     Q+     D   1

Excitation Table - TFF   Row     Q     Q+     T     1 2 3

Excitation Table - TFF Excitation tables are essentially rewriting the characteristic table of a flip flop so that Q and Q+ are "inputs" to the truth table. Q refers to the current state value  Q+ to the desired state value at the next positive clock edge   Row     Q     Q+     T   1 2 3

Finite State Machine If a combinational logic circuit is an implementation of a Boolean function, then a sequential logic circuit can be considered an implementation of a finite state machine. Q, a set of states S, an single state which is an element of Q. This is the start state. Input and outputs A transition function that maps a state and the input, to a state and an output.

FSM with Outputs Moore machines In this example, you see two bits for the state and two bits for the output. Thus, when you see 00/01 inside one of the circles, it is shorthand for q1q0 = 00 / z1 z0 = 01. A Moore machine has outputs that are a function of state

FSM with Outputs: Moore

FSM with Outputs: Moore

FSM with Outputs A Mealy machine has outputs that are a function of state and input

State Table – Sequential Circuit Design State Table describes a sequential circuit We want to go from a finite state machine that looks like: create a black box circuit that looks like:

State Table – Sequential Circuit Design Create a state transition table This is basically a truth table that records the information of the finite state machine. Decide how many flip flops you need, and what kind This is usually simple, because you have to encode each state of the finite state machine using ceil( lg( k ) ) bits. Or even better, someone's already given you an FSM with that information encoded. Choosing the kind of flip flop you want is usually an academic exercise. You'll often be told to use a certain flip flop, so you need to be able to handle the kind give. Use the flip flop excitation table, to fill out the rest of the chart. We'll talk about the excitation table momentarily. Implement the circuit using Flip Flops and Combinational Logic.