ECE - 1551 Digital logic Lecture 16: Synchronous Sequential Logic Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 10/27/2015

Recap Design Modeling using VHDL Introduction to Arithmetic Circuits. DataFlow Modeling Structural Modeling Behavioral Modeling. Introduction to Arithmetic Circuits. Half Adder Full Adder Binary Adder Ripple Adder Carry Look Ahead Logic BCD Adder Multiplier

Sequential Logic Sequential Logic: Where as Combinational Logic: 2018/9/21 Sequential Logic Sequential Logic: Output depends not only on current input but also on past input values, e.g., design a counter Need some type of memory to remember the past input values Where as Combinational Logic: Output depends only on current input Has no memory 2018/9/21 Sequential Circuits

Sequential Circuits Circuits that we Information Storing have learned 2018/9/21 Sequential Circuits Circuits that we have learned so far Information Storing Circuits Timed “States” 2018/9/21 Sequential Circuits

Combinational Circuits Sequential Logic Sequential Logic circuits remember past inputs and past circuit state. Outputs from the system are “fed back” as new inputs With gate delay and wire delay The storage elements are circuits that are capable of storing binary information: memory Most digital systems like handheld devices, cell phones, navigation receivers, digital watches, digital computers, digital traffic light controllers etc. require memory elements to store information. A sequential circuit is specified by a time sequence of inputs, outputs, and internal states Combinational Circuits Inputs Outputs Memory Elements

Storage Elements A storage element can maintain a binary state indefinetly, until directed by the input signal to switch states. Types of storage elements: Storage elements that operate with signal levels are referred as Latches. Storage elements that operate with signal transitions are referred as Flip Flops. Latches are said to be level sensitive devices; flip-flops are edge-sensitive devices. Flip flops are building blocks of Latches

SR Latch SR latch is an example of memory circuits that can store one bit of information When SR latch is storing a 1 then its Q is 1 and when storing 0 its Q is 0 SR latch is a circuit with two cross coupled NOR gates or two cross coupled NAND gates and two inputs labeled S and R for set and reset respectively. If SR=10 then Q=1 and the latch is storing a 1, We call this setting the Latch. If SR =10 and we change to SR=00 then the latch will remain set with Q= 1. In other words it "remembers" to stay set If SR=01 then Q=0 and the latch is storing a 0. We call this resetting or Clearing the latch If SR =01 and we change to SR=00 then the latch will remain set with Q= 0. We call the value of Q at any given time the state of the latch R Q S Q’

SR Gate level Implementation – With NOR gate The cross coupled NOR gates has feedback loop (from the output back to the input) If both S (set) and R (reset) are 1 an undefined state with both output equal to 0 occurs ( it means the SET and RESET commands are issuing at the same time). Forbidden

SR Gate level Implementation – With NAND gate The SR latch with two cross-coupled NAND gates. By setting S to 0 the output Q will be 1 that putting the latch in the set state If S goes to 1 the circuit remains in set state By setting R to 0 the circuit goes to reset state and stay there even after both input returns to 1 The undefined state is when both inputs are 0 Because NAND latch requires 0 signal to change its state it is also called S’-R’ latch

SR Latch (NAND version) 2018/9/21 SR Latch (NAND version) S’ R’ Q Q’ S’ 1 Q 0 0 0 1 1 0 1 1 1 0 Set Q’ 1 R’ X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 2018/9/21 Sequential Circuits

SR Latch (NAND version) 2018/9/21 SR Latch (NAND version) S’ R’ Q Q’ 1 S’ 1 Q 0 0 0 1 1 0 1 1 1 0 Set Q’ 1 1 0 Hold R’ X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 2018/9/21 Sequential Circuits

SR Latch (NAND version) 2018/9/21 SR Latch (NAND version) S’ R’ Q Q’ 1 S’ Q 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ 1 0 Hold R’ X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 2018/9/21 Sequential Circuits

SR Latch (NAND version) 2018/9/21 SR Latch (NAND version) S’ R’ Q Q’ 1 S’ Q 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ 1 R’ 1 0 Hold 0 1 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 2018/9/21 Sequential Circuits

SR Latch (NAND version) 2018/9/21 SR Latch (NAND version) S’ R’ Q Q’ S’ 1 Q 1 1 Disallowed 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ 1 0 Hold R’ 0 1 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 2018/9/21 Sequential Circuits

SR Latch Gate level Implementation – With NAND gate The operation of the basic SR latch can be modified by providing an additional input signal that determines (controls) when the state of the latch can be changed by determining whether S and R (or S and R ) can affect the circuit. Latch is sensitive to input changes ONLY when C=1 When the enable input goes to 1, information from the S or R input is allowed to affect the latch.

D Latch (Transparent Latch) D latch is designed to eliminate the indeterminate state in SR latch by making sure that inputs S and R are never equal to 1 at the same time

Graphic Symbols of Latches

Synchronous vs. Asynchronous There are two types of sequential circuits: Synchronous sequential circuit: circuit output changes only at some discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. Asynchronous sequential circuit: circuit output can change at any time (clockless). In Synchronous Systems: The flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram

Combinational Circuit Clock Period FF FF Combinational Circuit FF Smallest clock period = largest combinational circuit delay between any two directly connected FF, subjected to impact of FF setup time. 2018/9/21 Sequential Circuits

Flip Flop Latches are “transparent” (= any change on the inputs is seen at the outputs immediately when C=1). This causes synchronization problems. Solution: use latches to create flip-flops that can respond (update) only on specific times (instead of any time). Types: RS flip-flop, D flip-flop, JK FF and T flip flop.

Master-Slave FF configuration using SR latches

D – Flip Flop with MASTER and SLAVE Configuration The construction of a D flip-flop with two D latches and an inverter is shown in Fig. The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative edge of the synchronizing or controlling clock (designated as Clk ).

D-FF using 3 SR Latches Another construction of an edge-triggered D flip-flop uses three SR latches as shown in Fig. Two latches respond to the external D (data) and Clk (clock) inputs. The third latch provides the outputs for the flip-flop. when the input clock in the positive-edge- triggered flip-flop makes a positive transition, the value of D is transferred to Q . A negative transition of the clock (i.e., from 1 to 0) does not affect the output, nor is the output affected by changes in D when Clk is in the steady logic-1 level or the logic-0 level. Hence, this type of flip- flop responds to the transition from 0 to 1 and nothing else.

D – Flip Flop with MASTER and SLAVE Configuration

Other Flip Flops JK Flip Flop The JK flip-flop is an SRFF with some additional gating logic on the inputs in which the SR=11 (undetermined condition) doesn’t exist J is used for the set and K is used for reset clk J K Qn+1 ---------------------------- 0 X X Qn 1 0 0 Qn 1 0 1 0 1 1 0 1 1 1 1 Qn’

Other Flip Flops JK Flip Flop and Toggle Flip Flop. J Q clk K Q’

Other Flip Flops JK Flip Flop and Toggle Flip Flop. 1 1 J Q 1 clk K Q’ K Q’ Clk J K Qn+1 ------------------------- 1 1 0 1

Other Flip Flops JK Flip Flop and Toggle Flip Flop. 1 J Q 1 clk K Q’ J Q 1 clk K Q’ Clk J K Qn+1 ------------------------- 1 0 0 Qn

Other Flip Flops JK Flip Flop and Toggle Flip Flop. J Q 1 clk 1 1 K Q’

Other Flip Flops JK Flip Flop and Toggle Flip Flop. J Q 1 clk 1 K Q’ J Q 1 clk 1 K Q’ Clk J K Qn+1 ------------------------- 1 0 0 Qn

Other Flip Flops JK Flip Flop and Toggle Flip Flop. 1 J Q 1 clk 1 K Q’ Clk J K Qn+1 ------------------------- 1 1 1 Qn’

Toggle Flip Flop Toggle Flip flop is a special case where we connect J and K input together. clk J K Qn+1 ---------------------------- 0 X X Qn 1 0 0 Qn 1 1 1 Qn’

Other Flip Flop design using DFF In the design of VLSI circuits that contains millions of gates, the most commercial and efficient flip flop for these designs is the edge triggered D Flip Flop. Other types of flip flops can be constructed using D FF. Over all 3 operations that can be performed with a flip flop Set it to 1 Reset it to 0 Compliment its output. DFF performs first two operations, JK performs all three operations and TFF performs 3rd operation.

JK FF and Toggle FF using D-FF D = JQ’+K’Q J = 1 K = 0 D = Q’+Q = 1 J=0 K=1 D =0 J=K=1 D=Q’ J=K=0 D =Q T FF: D = Q xor T T = 1 D = Q’ T=0 D =Q

Characteristics Table / Function Table It is used to describe flip flop logical properties of a flip flop by describing its operation in a tabular form. Q(t+1) is the next state and Q(t) is the current state. J K Q (t+1) D Q (t+1) T Q(t+1) ------------------- ------------------- ------------------- 0 0 Q(t) 0 0 0 Q(t) 0 1 0 1 1 1 Q’(t) 1 0 1 1 1 Q’(t)

Characteristics Equation D-FF Characteristic table can be expressed algebraically with a characteristic equation. For the D-FF we have Q(t+1) = D It means that the next state of the output will be equal to value of D in the present state. JK-FF Q(t+1) = J Q’(t) + K’ Q(t)

Characteristics equation for JK Q(t) Q(t+1) 1 Q(t+1) = m1+mm4+m5+m6 Q(t+1) = J Q’(t) + K’ Q(t)

Direct Inputs The inputs that set the flip flop to 1 is called preset or direct set. The inputs that set the flip flop to 0 is called clear or direct reset. Clr clk D Q Q’ X 1 Rising edge Data D Q clk Clr

Applications of these FFs Frequency Divider and Counter using JK FF.