Sequential Circuits: Flip-Flops Digital Systems Section 10 Sequential Circuits: Flip-Flops

Lecture Digital Systems Clock Signals Digital systems can operate either asynchronously or synchronously. In asynchronous systems, the outputs of logic circuits can change state any time one or more of the inputs change. In synchronous system, the exact times at which any output can change states are determined by a signal commonly called as the enable/control or the clock. Enable/control is used in latch circuit. The inputs can affect the output only when the enable/control signal has a certain value. Clock is used in flip-flop circuit. The inputs can affect the output only when the clock signal changes (rising/positive edge or falling/negative edge).

Symbol of edge transition: triangle Lecture Digital Systems Clock Signals The clock signal is generally a rectangular pulse sequence. The clock signal is distributed to all parts of the system. All the system outputs can change state only when the clock makes a transition. When the clock goes from 0 to 1, this is called positive-edge transition; when the clock goes from 1 to 0, it is called negative-edge transition. Symbol of edge transition: triangle

Implementation of Edge Detector Lecture Digital Systems Implementation of Edge Detector The gate delay of an inverter (a few nanoseconds) is utilized to produce a pulse for a short time during and after the clock signal change. Assumption: Gate-delay of the NOT gate is significantly greater than the gate delay of the AND gate.

Implementation of Edge Detector Lecture Digital Systems Implementation of Edge Detector Because the clock signal is high only for a few nanoseconds, Q is affected by the levels at S and R only for a short time, during and after the occurrence of the active edge of the clock. See the R-S flip-flop made of the edge detector, gate circuit (pulse-steering circuit), and NAND latch above. If Clock = 0, then S’ = 1 and R’ = 1. The NAND latch is in “no change” state.

Setup Time and Hold Time Lecture Digital Systems Setup Time and Hold Time In practical circuits, it is essential to take the effects of propagation delays in to account. The input signal must be stable for a certain amount of time, before and after the clock change. Setup time (tsu): the minimum time that the input signal must be stable prior to the edge of the clock signal. Hold time (th): the minimum time that the input signal must be stable after the edge of the clock signal.

Lecture Digital Systems Flip-Flops A flip-flop is a storage element based on the gated latch principle. The output of a flip-flop output depends on the clock signal. Flip-flops are edge-triggered: output changes happen only when the active edge of the clock occurs. The active edge can be positive-edge (clock change from low to high) or negative-edge (clock change from high to low). Flip-flops can be built from one gated latch or two latches (i.e., master-slave flip-flop). Master-slave flip-flops: consist of 2 latches, output changes in every full cycle of the clock. In one half-cycle, the master is active and the input is acquired, in the other half-cycle, the slave is active and the input is delivered to the output.

D Flip-Flop (Positive-Edge) Lecture Digital Systems D Flip-Flop (Positive-Edge) This flip-flop is made of a gated D latch. The control signal is replaced by a clock signal (Clk). This flip-flop stores a value on the positive edge of Clk. Input that changes at any other times have no effect on the output. 9

Comparing D Latch and D Flip-Flops Lecture Digital Systems Comparing D Latch and D Flip-Flops D latch D flip-flop, Positive-Edge Triggered D flip-flop, Negative-Edge Triggered

Positive- and Negative-Edge D Flip-Flop Lecture Digital Systems Positive- and Negative-Edge D Flip-Flop D flip-flop can be triggered on positive- or negative-edge. The notations for both flip-flops are shown below. D Flip-flop, Negative-Edge Triggered D Flip-flop, Positive-Edge Triggered D Q Q’ D Q Q’ high to low low to high 11

Lecture Digital Systems D Flip-Flops

S-R Flip-Flop (Positive-Edge) Lecture Digital Systems S-R Flip-Flop (Positive-Edge)

S-R Flip-Flop (Negative-Edge) Lecture Digital Systems S-R Flip-Flop (Negative-Edge) Complete the time graph

Master-Slave D Flip-Flop Lecture Digital Systems Master-Slave D Flip-Flop Two D latches combined together plus a clock inversion form a master-slave D flip-flop. Only one C value is active at a time. When C = 1, Master is active  Y = D Slave is inactive  Q = previous value (held). When C = 0, Master is inactive  Y = previous value (held) Slave is active  Q = Y The output changes on the falling edge of the clock. Characteristic table / D C Q Q’ 1 Master-Slave D Flip-flop, Negative-Edge Triggered D Q Q’

Master-Slave D Flip-Flop Lecture Digital Systems Master-Slave D Flip-Flop Timing diagram Master-Slave D Flip-flop, Negative-Edge Triggered D Q Q’

Master-Slave S-R Flip-Flop Lecture Digital Systems Master-Slave S-R Flip-Flop In order to solve the hazard/ glitch problem, consider two R-S latches combined together. Only one Clk signal is active at a time. The inputs (S and R) will be taken by the master when the clock signal for the master is high. The outputs (Q and Q’) will be updated when the clock signal for the slave is high. S R Q Q’ Clk Clock S-R latch (Master) S-R latch (Slave) Output Input S Q Q’ R Master-Slave S-R Flip-flop, Negative-Edge Triggered

Positive-Edge J-K Flip-Flop Lecture Digital Systems Positive-Edge J-K Flip-Flop This J-K flip-flop is created from a D flip-flop. (But remember also that D flip-flop is made R-S latch). The input J and K is gated to produce D, with the equation: D = JQ’ + K’Q. The sequential operation of the J-K flip-flop is exactly the same as for the R-S flip-flop. The difference is that the J-K flip-flop has no invalid input.

Positive-Edge J-K Flip-Flop Lecture Digital Systems Positive-Edge J-K Flip-Flop Characteristic table Unchanged 1 K C Q Q’ Toggle J If J = 0, K = 0, then the output will stay the same. If J = 0, K = 1, then the output is reset (low). If J = 1, K = 0, then the output is set (high). If J = 1, K = 1, then the output is inverted/toggled.

Positive-Edge J-K Flip-Flop Lecture Digital Systems Positive-Edge J-K Flip-Flop Two data inputs, J and K J -> set, K -> reset, if J=K=1 then toggle output 20

Lecture Digital Systems J-K Flip-Flop

Exercise: Another J-K Flip-Flop Implementation Lecture Digital Systems Exercise: Another J-K Flip-Flop Implementation Find the characteristic table of the following implementation of J-K flip-flop, which is built from a NOR S-R latch. K J C Q Q’ R S J = 0, K = 0, Q = 1  S = 0, R = 0  Q = 1 Q = 0  S = 0, R = 0  Q = 0 J = 0, K = 1, Q = 1  S = 0, R = 1  Q = 0 J = 1, K = 0, Q = 1  S = 0, R = 0  Q = 1 Q = 0  S = 1, R = 0  Q = 1 J = 1, K = 1, Q = 1  S = 0, R = 1  Q = 0 Characteristic table of S-R latch

Positive-Edge T Flip-Flop Lecture Digital Systems Positive-Edge T Flip-Flop T (Toggle) flip-flop can be made of a D flip-flop or a J-K flip-flop. T flip-flop made of D flip-flop T flip-flop made of J-K flip-flop T flip-flop If T = 0, the output will stay. If T = 1, the output will be inverted/ toggled. Characteristic table Unchanged Toggle 1 T C Q Q’

Positive-Edge T Flip-Flop Lecture Digital Systems Positive-Edge T Flip-Flop Timing diagram Characteristic table Unchanged Toggle 1 T C Q Q’

Flip-Flop Excitation Table Lecture Digital Systems Flip-Flop Excitation Table An excitation table describes the state transition of a flip-flop. It shows the inputs to the flip-flop that are necessary to generate a particular next state (in other words, to excite it to the next state) when the current state is known. Excitation tables are similar to characteristic tables, but rearrange the data so that the current state and next state are next to each other on the left-hand side of the table, and the inputs needed to make that state change happen are shown on the right side of the table. Excitation table will be used when designing a circuit by flip-flop.

Flip-Flop Excitation Table Lecture Digital Systems Flip-Flop Excitation Table Q Qnext S R X 1 Q Qnext J K X 1 S-R Flip-Flop J-K Flip-Flop Q Qnext D 1 Q Qnext T 1 D Flip-Flop T Flip-Flop

Flip-Flop Characteristic Table (Revisited) Lecture Digital Systems Flip-Flop Characteristic Table (Revisited) S R Q Qnext 1 inv J K Q Qnext 1 D Q Qnext 1 D Flip-Flop T Q Qnext 1 S-R Flip-Flop J-K Flip-Flop T Flip-Flop

Creating A Flip-Flop from Another Flip-Flop Lecture Digital Systems Creating A Flip-Flop from Another Flip-Flop Utilizing the excitation table, perform the detailed steps to create a J-K flip-flop from a D flip-flop. Prove the correctness of circuit given before. J K Q Qnext 1 D 1 D ? Q Qnext D 1 D FF Excitation Table J-K FF Characteristic Table Required Input for D FF

Creating A Flip-Flop from Another Flip-Flop Lecture Digital Systems Creating A Flip-Flop from Another Flip-Flop Utilizing the excitation table, perform the detailed steps to create a J-K flip-flop from a D flip-flop. Prove the correctness of circuit given before. Connecting the inputs J, K, and Q with D, and simplifying them by using K-map: Q JK 1 00 01 11 10 K’Q In order to make a D flip flop behaves like a J-K flip-flop, D must be connected with J and K as: D = JQ’ + K’Q JQ’ K-map for D

Group Class Assignment Lecture Digital Systems Group Class Assignment Perform the detailed steps to create a T flip-flop from an S-R flip-flop. Further, construct your circuit in Atanua to prove its correctness. For inputs, use switch. For clock, use button (value high only when pressed) Save the result file (***.atanua) and send to my email address sitompul@president.ac.id. Title of email: Digital Systems, Class Number, Group Number. Body of email: Group members who present in class.

X X X X X X X November Schedule IT-2 W8 (14:30) W9 (14:30) W10 (07:30) Lecture Digital Systems November Schedule IT-2 W8 (14:30) W9 (14:30) W10 (07:30) X X X X X X X W11 (14:30)  Quiz 2 W12 (14:30)

X X X X X X X November Schedule IT-1 W8 (07:30) W9 (07:30) W10 (14:30) Lecture Digital Systems November Schedule IT-1 W8 (07:30) W9 (07:30) W10 (14:30) X X X X X X X W11 (07:30)  Quiz 2 W12 (07:30)

Lecture Digital Systems Group Homework 8 (1/2) For the S-R flip-flop shown below, plot the output signal Q for the given Set, Reset, and Clock signals. Assume that the initial value of Q is zero.

Lecture Digital Systems Group Homework 8 (2/2) Perform detailed steps to create a D flip-flop and J-K flip-flop using a single T flip-flop. Hint: Complete the following table. Fill the expected Qnext for the characteristic tables of the target flip-flop and use the excitation table of T flip-flop to find the required value for T. Then, find the circuit/equation to connect D and Q to T; or, respectively; J, K, and Q to T. Qnext D Q T 1 Qnext J Q T K 1 Please write your Class number after your Student ID. Deadline: 1 day before class. Friday, 10 November 2017 (Class 2). Friday, 10 November 2017 (Class 1).