Princess Sumaya University 4241 - Digital Logic Design ELEC203- Digital Logic Design Chapter 5: Synchronous Sequential Logic Dr. Bassam Kahhaleh

Flip-Flop Characteristic Tables and Equations Q(t+1) 1 Q(t+1) = D J K Q(t+1) Q(t) 1 Q’(t) J Q K Q(t+1) = JQ’ + K’Q T Q T Q(t+1) Q(t) 1 Q’(t) Q(t+1) = T  Q

Analysis of Clocked Sequential Circuits Characteristic and input equations A(t+1) = DA Char. Equ. DA = A x + B x Input equ. B(t+1) = DB Char. Equ. DB = A’ x Input equ. y(t) = (A + B) x’ A(t+1) = A x + B x State equ. B(t+1) = A’ x y(t) = (A + B) x’

Continue with solution , D Flip Flop State Table (Transition Table) State Diagram Present State Input Next State Output A B x y 1 0 0 0 0 1 0 0 0 1 1 1 0 1 0 0 t t+1 t

Summary on previous lecture 1- What is the sequential logic circuit, and we said it consists of Flip Flops and Combinational logic circuit. 2- There are two important topics in sequential logic circuits a) analysis of the circuit sequential logic cct state diagram b) synthesis of the circuit state diagram sequential logic cct 3- We discussed the steps of analysis procedure 4- Finally, we solved an example to analyze Seq. circuit analysis Synthesis (Design)

Outcomes of the lecture Lecture of today will consist of the following topics First Hour Deeper Understanding the analysis of the Sequential logic circuits by solving more problems a) D Flip Flop Circuit b) T Flip Flop Circuit c) JK Flip Flop Circuit (Assignment), solved later in the tutorial class Second Hour Understanding the synthesis ( Design) of the Sequential logic circuit 1) Explain the steps of synthesis procedure 2) Solve problems to cover the subject a) D Flip Flop Circuit b) JK Flip Flop Circit c) T Flip Flop Circuit (Assignment), solved later in the tutorial class

Reminder : Analysis of Sequential logic Circuit Char. Equation + Input Equation State Equation State diagram State table

Reminder: Flip-Flop Characteristic Tables and Equations Q(t+1) 1 Q(t+1) = D J K Q(t+1) Q(t) 1 Q’(t) J Q K Q(t+1) = JQ’ + K’Q T Q T Q(t+1) Q(t) 1 Q’(t) Q(t+1) = T  Q

Analysis of Clocked Sequential Circuits, Example D Flip-Flops Char. Equation A(t+1)= DA D Q x CLK y A Present State Input Next State A x y 1 DA = A  x  y input equ. A(t+1) =DA = A  x  y state equ. 1 01,10 1 00,11 00,11 01,10

Summary of solution D Flip-Flops Input Equation DA = A  x  y Char. Equation A(t+1)= DA + State Equation A(t+1) =DA = A  x  y State diagram HW : Solve this problem using T FF State table

Analysis of Clocked Sequential Circuits T Flip-Flops , Char. Equ. A(t+1) = Ta A’ + T’a A B(t+1) = Tb B’ + T’b B Present State I/P Next State O/P A B x y 1 0 0 0 1 1 0 1 1 0 0 1 1 Input Equ. Ta = B x Tb = x y = A B State Equ. A(t+1) = AB’ + Ax’ + A’Bx B(t+1) = x  B

Continue with solution , Analysis – T Flip Flop State Dagram State Table

Summary of solution T Flip-Flops Char. Equ. A(t+1) = Ta A’ + T’a A B(t+1) = Tb B’ + T’b B Input Equ. Ta = B x Tb = x y = A B + State Equ. A(t+1) = AB’ + Ax’ + A’Bx B(t+1) = x  B State diagram State table

Analysis of Clocked Sequential Circuits, Practice at home JK Flip-Flops Char. equations A(t+1) = JA A’ + K’A A B(t+1) = JB B’ + K’B B Input Equations JA = B KA = B x’ JB = x’ KB = A  x State Table State equations A(t+1) = A’B + AB’ + Ax B(t+1) = B’x’ + ABx + A’Bx’

Continue with solution , Analysis JK Flip Flop State Table Present State I/P Next State A B x 1 State Diagram 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1

Summary of solution JK Flip-Flops Char. equations A(t+1) = JA A’ + K’A A B(t+1) = JB B’ + K’B B Input Equations JA = B KA = B x’ JB = x’ KB = A  x + State equations A(t+1) = A’B + AB’ + Ax B(t+1) = B’x’ + ABx + A’Bx’ State diagram State table

Assignment For analysis of Sequential logic circuit

Synthesis of Sequential Logic Circuits

Steps of sequential Flip Flop circuit Synthesis 1- Study the problem 2- Draw the state diagram (if not available) 3- Build the state table 4- Choose the Flip Flop type( D , T , or JK) 5- Build the Full Excitation Table by adding new columns to the state table. These new columns are equal to the number of the FFs in the circuit. 6- From the Full Excitation Table , we will find the input equations and output function (if any ) using K-map. 7- Draw the Sequential Logic Circuit

Synthesis of synchronous circuits Basic Excitation Tables for FFs Present State Next State F.F. Input Q(t) Q(t+1) J K 1 Present State Next State F.F. Input Q(t) Q(t+1) D 1 1 0 x 1 x x 1 x 0 Q(t) Q(t+1) T 1 1

Synthesis of synchronous circuits Example 1 State Diagram Step 1 &2

Synthesis of synchronous circuits Step 3 State Table

Synthesis of synchronous circuits Sep 4 & 5 Full Excitation Table W select T type FF

Synthesis of synchronous circuits ∑ ∑ ∑ Synthesis of synchronous circuits ∑ (3,7) ∑(1,3,5,7) BX BX A A TA = B x TB = x y = A B Step 6 & 7

Summary of solution , Synthesis – T Flip Flop

Design of Clocked Sequential Circuits with JK F.F. Synthesis using JK F.F. Present State Input Next State Flip-Flop Inputs A B x JA KA JB KB 1 JA (A, B, x) = ∑ (3) dJA (A, B, x) = ∑ (4,5,6,7) KA (A, B, x) = ∑ (4, 6) dKA (A, B, x) = ∑ (0,1,2,3) JB (A, B, x) = ∑ (1, 5) dJB (A, B, x) = ∑ (2,3,6,7) KB (A, B, x) = ∑ (2, 3, 6) dKB (A, B, x) = ∑ (0,1,4,5) 0 x 1 x x 1 x 0 0 x 1 x x 1 x 0

Design of Clocked Sequential Circuits with JK F.F. Synthesis using JK Flip-Flops JA = B x KA = x’ JB = x KB = A’ + x’ B 1 A x B x A 1 B 1 x A B x 1 A

Design of Clocked Sequential Circuits with T F.F. Solve the problem using T FF Present State Input Next State F.F. A B x TA TB 1 1 1 Synthesis using T Flip-Flops TA (A, B, x) = ∑ (3, 4, 6) TB (A, B, x) = ∑ (1, 2, 3, 5, 6)

Design of Clocked Sequential Circuits with T F.F. Synthesis using T Flip-Flops TA = A x’ + A’ B x TB = A’ B + B  x B 1 A x B 1 A x

Design of Clocked Sequential Circuits Solve the Same problem using D FF Present State Input Next State Output A B x y 1 00 01 11 10 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1

Design of Clocked Sequential Circuits Present State Input Next State Output A B x y 1 Synthesis using D Flip-Flops 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 A(t+1) = DA (A, B, x) = ∑ (3, 5, 7) B(t+1) = DB (A, B, x) = ∑ (1, 5, 7) y (A, B, x) = ∑ (6, 7)

Design of Clocked Sequential Circuits with D F.F. Synthesis using D Flip-Flops B 1 A x DA (A, B, x) = ∑ (3, 5, 7) = A x + B x DB (A, B, x) = ∑ (1, 5, 7) = A x + B’ x y (A, B, x) = ∑ (6, 7) = A B B 1 A x B A 1 x

Design of Clocked Sequential Circuits with D F.F. Synthesis using D Flip-Flops DA = A x + B x DB = A x + B’ x y = A B

Homework Mano Chapter 5 5-1 5-3 5-6 5-8 5-9

Homework 5-1 The D latch is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. (a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed. (b) Use NOR gates for all four gates. Inverters may be needed. (c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate that goes to the SR latch to the input of the lower gate instead of the inverter output.

Homework 5-3 Show that the characteristic equation for the complement output of a JK flip-flop is Q’(t+1) = J’Q + K Q 5-6 A sequential circuit with two D flip-flops, A and B; two inputs, x and y; and one output, z, is specified by the following next-state and output equations: A(t+1) = x’ y + x A B(t+1) = x’ B + x A z = B (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.

Homework 5-8 Derive the state table and the state diagram of the sequential shown circuit. Explain the function that the circuit performs.

Homework 5-9 A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations: JA = x KA = B’ JB = x KB = A (a) Derive the state equations A(t+1) and B(t+1) by substituting the input equations for the J and K variables. (b) Draw the state diagram of the circuit.