DIGITAL ELECTRONICS ТHEME 4: SEQUENTIAL LOGIC CIRCUITS. FLIP- FLOPS – ASYNCHRONOUS AND SYNCHRONOUS, R - S, D, T, J - K FLIP- FLOPS. The value of the outputs of sequential logic devices (SLD) at a moment t depend on the values of the input variables at the same moment as well as the state of the device in the previous moment (t-1). That means that these devices have memory elements which memorize the inner state of the device. A sequential circuit can be treated as constructed of two parts – a combinational logic circuit (CLC) and a memory part as shown in figure. A SLC is completely defined if the following parameters are given: the set of input variables – Х; the set of output functions – Y; the set of inner states of the device – А; the function of the transitions – with generalized type: Аt+1=F(At, Xt); the function of the outputs – with generalized type: Yt= F1(At) или Yt= F2(At, Xt); The SLC are divided in two groups according to the function of the outputs: Moore automaton – the state of the outputs coincide with the inner state of the SLC; Mealy automaton. CLC MEMORY X Y A General structure of CLC.

DIGITAL ELECTRONICS The simplest SLC which are used for building more complex SLC are the flip-flops. They are SLC with two stable states – “1” and “0” – the flip-flop is the simplest memory cell with 1 bit volume. Every flip-flop has two outputs – a main (direct) output and a complementary (inverse) one. The value of the complementary output is inverse to the direct output. They are marked with Q andQ respectively. The flip-flops are divided in two groups according to the mode of operation: asynchronous (latch) – the input signal affects the flip-flop at the moment they are fed; synchronous flip –flop - the input signal affects the flip-flop only during the action of a special enabling signal called synchronizing (C - Clock) or (T) signal. The synchronous flip-flops can be divided in three groups: clock controlled flip-flops (gated latch) – the switching takes place during the enabling (clock) signal; edge switched flip-flops (dynamic flip-flop) – they switch during the edge of the clock signal (the transition from logic level “0” to “1“ is called leading (positive) transition (edge) () and transition from “1” to “0” is called trailing (negative) transition (edge) (); master-slave flip-flops in which an intermediate memorizing of the input signal is used.

DIGITAL ELECTRONICS Master-slave flip-flops are two stages flip-flops which work synchronously. During the active level of synchronizing signal the input stage accepts the input signals. At the same time the output stage is forbidden. When the synchronizing signal goes in passive level then the signals are transferred from input to the output stage. In functional aspect and according to the number of inputs the flip-flops are divided on: R-S, D, J-K, T. The R-S type flip-flop has two inputs. The S input sets the flip-flop in state “1” and the R input sets the flip-flop in state “0”. At least one of the inputs must be “0” for the correct function of the device. This is expressed by the logic function R.S = 0. The set R=S=1 is not allowed (forbidden) because the main logic of ordinary function of the flip-flop is disturbed. When the forbidden set is fed both outputs go in state “0”. Feeding allowed set R=S=’0’ immediately after that will cause signal racing and it will not be clear how the flip-flop will be set. There are equal probabilities the flip-flop to be set in “0” or in “1” state. An asynchronous flip-flop can be realized with two Logic gates NOR as shown on the left side of the figure below. For realization of the other types of flip-flops often is used a flip-flop with inverse inputs – the so called R -S flip-flop where the active level of the inputs is “0”. An asynchronous R -S flip-flop can be realized with NAND elements, as shown on the right side of the figure below.

DIGITAL ELECTRONICS The functional behavior of the R-S type flip-flop could be described by the Transition table or by the following analytical expression: R S Qt Qt+1 Qt+1 1 R S Q Asynchronous R-S and R-S flip-flops, realized with logic gates.

DIGITAL ELECTRONICS Clock controlled R-S flip-flop can be realized by adding two NAND gates to the inputs of R-S type flip-flop and then the R and S signals will be fed to the inputs only during the active level of the clock signal (С). The D – type flip-flop has only one input marked as D (from delay) and the output repeats the input signal with a delay of one cycle. It means that the level of the direct output Q at the moment of time (t+1) coincides with the level of input D at the moment (t). R S Q С D Q С Asynchronous and synchronous D-type flip-flops, realized with logic gates. Synchronous R-S flip-flop.

DIGITAL ELECTRONICS The functional behavior of the D- type flip-flop could be described by the Transition table or by the following analytical expression: D Qt Qt+1 Qt+1 1 The J-K– type flip-flop has two inputs. The input J is equivalent to the S input and the K input is equivalent to the R input of R-S flip-flop. The difference here is that all the sets of input signals are allowed. When J = K = 1 combination is fed to the inputs, the value of the output is changed – it acts as T – type flip-flop. The functional behavior of the J-K - type flip-flop could be described by the Transition table or by the following analytical expression: C J K Qt Qt+1 Qt+1  1

DIGITAL ELECTRONICS Synthesis of J-K -type from R-S –type flip-flops (the second is a master-slave structure). The T – type flip-flop has one input, marked as T. When a signal is fed to the input the value of the output is changed. Because of this the T-type flip-flop is used as a frequency divider – it divides the frequency of the input signal by 2. These flip-flops are used also for building binary counters. The functional behavior of the T - type flip-flop could be described by the Transition table or by the following analytical expression: Т Qt Qt+1 Qt+1 1

DIGITAL ELECTRONICS The T-type flip-flops are not produced as IC. Usually a D or a J-K flip-flop is used for realizing T – type flip-flop. A D –type flip-flop will work as a T-type flip-flop if the inverse outputQ is connected to the D input and the clock input ( C ) is used as a T input. To realize T-type flip-flop with J-K one it is necessary to feed “1” to both inputs (J and K) and again the clock input ( C ) is used as a T input. Synthesis of T – type from synchronous D – type or from J-K –types flip-flops. Using flip-flops it is very important to know their timing parameters. The main ones are illustrated by the following time-diagrams:

Main time-diagrams and timing parameters of the flip-flops. DIGITAL ELECTRONICS Main time-diagrams and timing parameters of the flip-flops. ts – set-up time. This is the time preceding the clock pulse, during which the inputs must be settled; th – hold time. This is the time succeeding the active edge of the clock pulse during which the input signals must stay unchanged; tQ – propagation delay time. This is the time passed after the active edge of the clock pulse till receiving the new valid signals on the outputs; tw – minimum pulse width; Fmax – maximum switching frequency for proper work of the flip-flop.