Nanowire Gate-All-Around (GAA) FETs Siyu Liu Mar. 7th, 2018

Short channel effect and device structure solution In electronics, short-channel effects occur in MOSFETs in which the channel length is comparable to the depletion-layer widths of the source and drain junctions. Short-channel effects include, in particular, drain-induced barrier lowering, velocity saturation, and hot carrier degradation. shows the evolution of multiple-gate transistors schematically in the order of increasing gate electrostatic control. Progression of device structure

Why Gate-All-Around (GAA)? Scaling factor: 𝛼= 𝐿 𝑒𝑓𝑓 2𝜆 Double Gate MOSFET  the total power consumed per unit area remain constant. Although the requirements on the ratio between Leff and 𝜆 would depend on the specific application, y = LCff/𝜆 = 5 -10 is generally enough to produce reasonable subthreshold behavior. This means that, for the same effective channel length this structure would have better subthreshold behavior than the structure of Fig. 3 (or Fig. 5(a)). The minimum channel length for good subthreshold characteristics can thus be made about 30% shorter by going from the conventional SO1 structure to Gate-All-Around. GAA MOSFET Auth, Christopher P., and James D. Plummer. "Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's." IEEE Electron Device Letters 18.2 (1997): 74-76.

Fabrication Methods Bottom Up Top Down [1] Tanaka, Tomotaka, et al. "Vertical surrounding gate transistors using single InAs nanowires grown on Si substrates." Applied physics express 3.2 (2010): 025003. [2] Gu, J. J., et al. "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach." Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE, 2011.

ss =ln10 𝑑 𝑉 𝐺𝑆 𝑑 (ln 𝐼 𝐷 ) Subthreshold swing Drain-induced barrier lowering (DIBL) The subthreshold swing is defined as the gate voltage required. to change the drain current by one order of magnitude, one. decade. In the MOSFET, thesubthreshold swing is limited. to (kT/q) ln10 or 60 mV/dec at room temperature. (k is Boltzmann’s constant, q is the electron charge, and T is the temperature). Drain-induced barrier lowering or DIBL is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages. ss =ln10 𝑑 𝑉 𝐺𝑆 𝑑 (ln 𝐼 𝐷 ) limited to (kT/q) ln10 or 60 mV/dec at room temperature

I-V curves of 3nm SiNW GAA MOSFETs with Lg =350nm. On-current Ids  (|Vd |=|Vg - Vth |=1.2V) of ~2.4mA/μm and ~1.3mA/μm are obtained for n- and p-FETs, respectively. Ion/Ioff  ratio >10^6 . Id -Vg  plot exhibits near-ideal SS (60mV/dec for n- and 65mV/dec for p-FET) low DIBL (6mV/V for n- and 13mV/V for p-FETs). Even for Lg =350nm, these Ids are higher than most of the earlier reports on nanowire devices with shorter gate lengths [8-9]. Singh, N., et al. "Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance." Electron Devices Meeting, 2006. IEDM'06. International. IEEE, 2006.

The impact of nanowire diameter on SS and DIBL Simply, for a given gate length, it is expected that as the channel body gets wider, the gate electrostatic control on the channel regions gets weaker in respect to the influence from the source/drain, just like for planar devices, so the SS and DIBL degrade with the increasing wire diameters. Yang, B., et al. "Vertical silicon-nanowire formation and gate-all-around MOSFET." IEEE Electron Device Letters 29.7 (2008): 791-794.

Gate-all-around (GAA) III-V MOSFETs  In0.53 Ga0.47 As channel and atomic-layer-deposited (ALD) Al2O3 /WN gate  Lch  = 50nm on-current of 720μA/μm, subthreshold swing (SS) of 150mV/dec drain-induced barrier lowering (DIBL) of 210mV/V. Gu, J. J., et al. "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach." Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE, 2011.

Gate-all-around (GAA) III-V MOSFETs  Fig. 16 benchmarks the gm ∙EOT product vs. Lch  of In0.53 Ga0.47 As GAA FETs with our previous work on InGaAs MOSFETs [1][9][11-13] . Despite the low indium concentration (53%), the In0.53 Ga0.47 As GAA MOSFETs show the highest gm ∙EOT product. Better on-state performance is expected on InGaAs GAA MOSFETs with higher indium content (65% to 75%), due to the higher electron mobility and the charge neutral level being closer to the conduction band edge. Table 2 compares the device structure and performance of In0.53 Ga0.47 As GAA FETs in this work with representative topdown non-planar III-V FETs [1-3][11] Due to the excellent electrostatic control of the channel by GAA structure, Lch  has been pushed down to 50nm with excellent on-state and reasonable off-state performance. Gu, J. J., et al. "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach." Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE, 2011.

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