Subject Name: Microprocesor Subject Code: 10CS45 Prepared By: Kavyashree.C Department: CSE Unit 2: Microprocessor Architecture -2 9/22/2018

Topic Details Protected Mode Memory addressing Program Invisible Registers Memory Paging Flat Mode Memory Model Data Addressing Modes Data Structures Program memory Addressing Modes Stack Memory Addressing modes 9/22/2018

PROTECTED MODE MEMORY ADDRESSING Allows access to data and programs located within & above the first 1M byte of memory. Protected mode is where Windows operates. In place of a segment address, the segment register contains a selector that selects a descriptor from a descriptor table. The descriptor describes the memory segment’s location, length, and access rights. 9/22/2018

Selectors and Descriptors The descriptor is located in the segment register & describes the location, length, and access rights of the segment of memory. it selects one of 8192 descriptors from one of two tables of descriptors In protected mode, this segment number can address any memory location in the system for the code segment. Indirectly, the register still selects a memory segment, but not directly as in real mode. 9/22/2018

Local descriptors are usually unique to an application. Global descriptors contain segment definitions that apply to all programs. Local descriptors are usually unique to an application. a global descriptor might be called a system descriptor, and local descriptor an application descriptor Figure shows the format of a descriptor for the 80286 through the Core2. each descriptor is 8 bytes in length global and local descriptor tables are a maximum of 64K bytes in length 9/22/2018

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The base address of the descriptor indicates the starting location of the memory segment. the paragraph boundary limitation is removed in protected mode segments may begin at any address The G, or granularity bit allows a segment length of 4K to 4G bytes in steps of 4K bytes. 32-bit offset address allows segment lengths of 4G bytes 16-bit offset address allows segment lengths of 64K bytes. 9/22/2018

Operating systems operate in a 16- or 32-bit environment. DOS uses a 16-bit environment. Most Windows applications use a 32-bit environment called WIN32. MSDOS/PCDOS & Windows 3.1 operating systems require 16-bit instruction mode. Instruction mode is accessible only in a protected mode system such as Windows Vista. 9/22/2018

Access rights byte The access rights byte controls access to the protected mode segment. describes segment function in the system and allows complete control over the segment if the segment is a data segment, the direction of growth is specified If the segment grows beyond its limit, the operating system is interrupted, indicating a general protection fault. You can specify whether a data segment can be written or is write-protected. 9/22/2018

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The TI bit selects either the global or the local descriptor table. Descriptors are chosen from the descriptor table by the segment register. register contains a 13-bit selector field, a table selector bit, and requested privilege level field The TI bit selects either the global or the local descriptor table. Requested Privilege Level (RPL) requests the access privilege level of a memory segment. If privilege levels are violated, system normally indicates an application or privilege level violation 9/22/2018

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Figure shows how the segment register, containing a selector, chooses a descriptor from the global descriptor table. The entry in the global descriptor table selects a segment in the memory system. Descriptor zero is called the null descriptor, must contain all zeros, and may not be used for accessing memory. 9/22/2018

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Program-Invisible Registers Global and local descriptor tables are found in the memory system. To access & specify the table addresses, 80286–Core2 contain program-invisible registers. not directly addressed by software Each segment register contains a program-invisible portion used in the protected mode. often called cache memory because cache is any memory that stores information 9/22/2018

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When a new segment number is placed in a segment register, the microprocessor accesses a descriptor table and loads the descriptor into the program-invisible portion of the segment register. held there and used to access the memory segment until the segment number is changed This allows the microprocessor to repeatedly access a memory segment without referring to the descriptor table. hence the term cache 9/22/2018

The GDTR (global descriptor table register) and IDTR (interrupt descriptor table register) contain the base address of the descriptor table and its limit. when protected mode operation desired, address of the global descriptor table and its limit are loaded into the GDTR The location of the local descriptor table is selected from the global descriptor table. one of the global descriptors is set up to address the local descriptor table 9/22/2018

To access the local descriptor table, the LDTR (local descriptor table register) is loaded with a selector. selector accesses global descriptor table, & loads local descriptor table address, limit, & access rights into the cache portion of the LDTR The TR (task register) holds a selector, which accesses a descriptor that defines a task. a task is most often a procedure or application Allows multitasking systems to switch tasks to another in a simple and orderly fashion 9/22/2018

MEMORY PAGING The memory paging mechanism allows any physical memory location to be assigned to any linear address. Iinear address is defined as the address generated by a program. Physical address is the actual memory location accessed by a program. With memory paging, the linear address is invisibly translated to any physical address. 9/22/2018

Paging Registers The paging unit is controlled by the contents of the microprocessor’s control registers. Beginning with Pentium, an additional control register labeled CR4 controls extensions to the basic architecture. See Figure for the contents of control registers CR0 through CR4. 9/22/2018

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Figure shows the linear address and its makeup for paging. The linear address, as generated by software, is broken into three sections that are used to access the page directory entry, page table entry, and memory page offset address. Figure shows the linear address and its makeup for paging. When the program accesses a location between 00000000H and 00000FFFH, the microprocessor physically addresses location 00100000H–00100FFFH. 9/22/2018

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The 80486 cache holds the 32 most recent page translation addresses. Intel has incorporated a special type of cache called TLB (translation look-aside buffer). because repaging a 4K-byte section of memory requires access to the page directory and a page table, both located in memory The 80486 cache holds the 32 most recent page translation addresses. if the same area of memory is accessed, the address is already present in the TLB This speeds program execution Pentium contains separate TLBs for each of their instruction and data caches. 9/22/2018

The Page Directory and Page Table Only one page directory in the system. The page directory contains 1024 doubleword addresses that locate up to 1024 page tables. Page directory and each page table are 4K bytes in length. 9/22/2018

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Flat Mode Memory A flat mode memory system is one in which there is no segmentation. does not use a segment register to address a location in the memory First byte address is at 00 0000 0000H; the last location is at FF FFFF FFFFH. address is 40-bits The segment register still selects the privilege level of the software. 9/22/2018

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DATA ADDRESSING MODES MOV instruction is a common and flexible instruction. provides a basis for explanation of data-addressing modes Source is to the right and destination the left, next to the opcode MOV. an opcode, or operation code, tells the microprocessor which operation to perform Mov destination, source 9/22/2018

Register Addressing The most common form of data addressing. once register names learned, easiest to apply. The microprocessor contains these 8-bit register names used with register addressing: AH, AL, BH, BL, CH, CL, DH, and DL. 16-bit register names: AX, BX, CX, DX, SP, BP, SI, and DI. MOV AX,BX MOV SP,BP MOV ECX,EBX 9/22/2018

Immediate Addressing Term immediate implies that data immediately follow the hexadecimal opcode in the memory. immediate data are constant data data transferred from a register or memory location are variable data Immediate addressing operates upon a byte or word of data. MOV AX,#3456H MOV SI,0 MOV CH,100 MOV AL,’A’ 9/22/2018

Direct Data Addressing Two basic forms of direct data addressing: direct addressing, which applies to a MOV between a memory location and AL, AX, or EAX Eg: MOV AL,DATA MOV AL,DS:[1234] displacement addressing, which applies to almost any instruction in the instruction set Eg: MOV CH,DOG MOV DATA,SP Address is formed by adding the displacement to the default data segment address or an alternate segment address. 9/22/2018

Register Indirect Addressing Allows data to be addressed at any memory location through an offset address held in any of the following registers: BP, BX, DI, and SI. In addition, 80386 and above allow register indirect addressing with any extended register except ESP. In the 64-bit mode, the segment registers serve no purpose in addressing a location in the flat model. 9/22/2018

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Base-Plus-Index Addressing Similar to indirect addressing because it indirectly addresses memory data. The base register often holds the beginning location of a memory array. the index register holds the relative position of an element in the array whenever BP addresses memory data, both the stack segment register and BP generate the effective address 9/22/2018

Register Relative Addressing Similar to base-plus-index addressing and displacement addressing. data in a segment of memory are addressed by adding the displacement to the contents of a base or an index register (BP, BX, DI, or SI) Figure 3–10 shows the operation of the MOV AX,[BX+1000H] instruction. A real mode segment is 64K bytes long 9/22/2018

Base Relative-Plus-Index Addressing Similar to base-plus-index addressing. adds a displacement uses a base register and an index register to form the memory address This type of addressing mode often addresses a two-dimensional array of memory data. 9/22/2018

Scaled-Index Addressing Unique to 80386 - Core2 microprocessors. uses two 32-bit registers (a base register and an index register) to access the memory The second register (index) is multiplied by a scaling factor. the scaling factor can be 1x, 2x, 4x, 8x A scaling factor of is implied and need not be included in the assembly language instruction (MOV AL,[EBX + ECX]). 9/22/2018

RIP Relative Addressing Uses the 64-bit instruction pointer register in the 64-bit mode to address a linear location in the flat memory model. Inline assembler program available to Visual does not contain any way of using this mode or any other 64-bit addressing mode. The Microsoft Visual does not at present support developing 64-bit assembly code. 9/22/2018

Data Structures Used to specify how information is stored in a memory array. a template for data The start of a structure is identified with the STRUC assembly language directive and the end with the ENDS statement. 9/22/2018

PROGRAM MEMORY-ADDRESSING MODES Used with the JMP (jump) and CALL instructions. Consist of three distinct forms: direct, relative, and indirect 9/22/2018

Direct Program Memory Addressing Used for all jumps and calls by early microprocessor; also used in high-level languages, such as BASIC. GOTO and GOSUB instructions The microprocessor uses this form, but not as often as relative and indirect program memory addressing. The instructions for direct program memory addressing store the address with the opcode. 9/22/2018

An intersegment jump is a jump to any memory location within the entire memory system Often called a far jump because it can jump to any memory location for the next instruction. The only other instruction using direct program addressing is the intersegment or far CALL instruction. 9/22/2018

Relative Program Memory Addressing The term relative means “relative to the instruction pointer (IP)”. The JMP instruction is a 1-byte instruction, with a 1-byte or a 2-byte displacement that adds to the instruction pointer. They are called intrasegment jump 9/22/2018

Indirect Program Memory Addressing In 80386 and above, an extended register can be used to hold the address or indirect address of a relative JMP or CALL. JMP AX; NEAR JUMP JMP TABLE[BX]; Table Plus BX JMP[BX}; indirect-indirect or double indirect jump 9/22/2018

STACK MEMORY-ADDRESSING MODES The stack plays an important role in all microprocessors. holds data temporarily and stores return addresses used by procedures Stack memory is LIFO (last-in, first-out) memory describes the way data are stored and removed from the stack 9/22/2018

Stack memory is maintained by two registers: Data are placed on the stack with a PUSH instruction; removed with a POP instruction. Stack memory is maintained by two registers: the stack pointer (SP or ESP) the stack segment register (SS) Whenever a word of data is pushed onto the stack, the high-order 8 bits are placed in the location addressed by SP – 1. low-order 8 bits are placed in the location addressed by SP – 2 9/22/2018

Not available on early 8086/8088 processors. PUSHA and POPA instructions push or pop all except segment registers, on the stack. Not available on early 8086/8088 processors. 80386 and above allow extended registers to be pushed or popped. 64-bit mode for Pentium and Core2 does not contain a PUSHA or POPA instruction A PUSHFD stores the EFLAGS, whereas a PUSHF stores the FLAGS. POPA and PUSHA are not available in 64-bit mode 9/22/2018

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