New Directions in the Development of ABC Alan Mishchenko Robert Brayton Department of EECS UC Berkeley

Overview What is beyond logic synthesis? Overview of recent research New (even more scalable) logic synthesis Formal verification High-level (in particular, word-level logic) synthesis Place and route Overview of recent research Linear-time algorithm for divisor extraction (IWLS’15) Reverse-engineering AIG into a word-level netlist (IWLS’15) Sequential verification after clock-gating (DAC’15) C-to-Verilog translation (IWLS’15) Focusing on two recent developments Handling word-level designs in ABC Formulating and solving problems using a QBF solver 2

Handling Word-Level Designs in ABC Structural Verilog ABC Structural Verilog parser Verific RTL Designs Programmable APIs RTL Industrial database Word-level netlist Bit-level engines Structural Verilog

Ongoing Work Developing a robust netlist data-structure to representing designs that are Structural should also handle “industrial stuff” (memories, flops, inouts, etc) Hierarchical should also be efficient for large flat objects Word-level should also allow for bit-level and byte-level handling Some interesting findings here

QBF What is QBF? Practical applications Problem representation QBF solver(s) in ABC Improving scalability

Background on SAT A typical SAT problem Given a set of constraints, find a solution Example: find a winning move of the game White begins and wins in 1 move

Extension to QBF What if we play against an opponent? Given the constraints, and the allowed moves for each player – find a winning strategy White begins and wins in 3 moves!

QBF Example: Consider it as a two player game E (a GOOD player) is trying to satisfy the problem A (a EVIL player) is trying to falsify it

Satisfiable QBF Consider instance It is SAT because there is a winning strategy for the E player (model):

Unsatisfiable QBF Consider instance It is UNSAT because there is a winning strategy for the A player (counter-model):

Application 1: Relation Determinization Given a relation, find its functional representation Existing approaches use BDD Has a natural QBF encoding

Application 2: BMC SAT encoding QBF High level info missing Semantically suppressed multiple copies of T 12

Application 3: Logic Synthesis Find a “parameterized” implementation = CNFization OR 2LUT AND 2LUT

Application 4: Invariant Computation Given relation R, compute invariant F Model invariant as a K-LUT with function specified by parameters p Joint work with Professor Fujita at U of Tokyo

QBF Problem Representation QBF miter Combinational circuit (an AIG) with one primary output Primary inputs are “parameter” and “functional variables” (“parameters” are ordered before “functional variables”) QBF solvers in ABC Commands “qbf” and “&qbf” Example: Finding an implementation of 6-input AND-gate in terms of 5 two-input AND-gates abc 01> gen -f -N 6 -K 2 -L 5 qbf/fpga_N6_K2_L5.blif abc 01> read qbf/fpga_N6_K2_L5.blif; ps; st; ps; &get; &qbf -P 60 Warning: The network contains hierarchy. Hierarchy reader flattened 15 instances of logic boxes and left 0 black boxes. struct5x2_6 : i/o = 66/ 1 lat = 0 nd = 183 lev = 41 struct5x2_6 : i/o = 66/ 1 lat = 0 and = 283 lev = 53 Parameters: 111011101101001001000001010100000100001001110011011010001001 Stats: 0=34 1=26 The problem is SAT after 26 iterations. Time = 0.07 sec

QBF Solvers in ABC QBF miters are solved by a CEGAR approach, which employs two SAT solvers One solver checks if a given p-valuation is a solution If the solver returns UNSAT, the QBF problem is SAT One solver looks for the next p-valuation to check If the solver returns UNSAT, the QBF problem is UNSAT Good scalability required efficient implementation Recently, we researched several new ways of scaling the QBF solver: Better CNF generation Better selection of p-valuations Selective quantification of functional variables

Conclusions Reviewed recent developments in ABC Focused on two new trends Inputting and using word-level design information Emergence of QBF solver as a practical tool in solving problems arising in synthesis and verification The current work is focusing on Improving word-level netlist data-structure Improving scalability of QBF solvers in ABC

Abstract In this presentation, we will review a number of new directions that are currently being explored in developing ABC. We will focus on two directions on interest to this group.  The first one is, adding capabilities to ABC for inputting word-level hierarchical design information, and their impact on integration with industrial tools.  The second one is, the emergence of QBF as a practical computation engine, scalability improvements to the QBF solver ABC, and practical applications in synthesis and verification.