Robust Window-based Multi-node Technology- Independent Logic Minimization Jeff L.Cobb Kanupriya Gulati Sunil P. Khatri Texas Instruments, Inc. Dept. of ECE, Texas A&M University 1

Overview Introduction Background Previous work Approach Experimental results Conclusions 2

Introduction VLSI design flow HDL (Verilog, VHDL) Logic optimization Physical design 3

Introduction Purpose of logic optimization Reduce area Reduce power Reduce delay Logic optimization Technology-independent optimization Goal: reduce literal count Technology-dependent optimization 4

Background Dont Cares Logic function allowed to have 0 or 1 as possible output for a given input ODCSDC XDC: External dont cares given 5

Background Dont Cares Computed for one node at a time Cannot capture multi-node flexibility 6 xy (x+y) = xy(xy) + (x+y)(x+y) = xy+xy = x y Goal: multi-node logic minimization Yields a Boolean relation Need to determinize this relation for solution

Background Boolean relations Can express more than one allowed output vector for a single input vector Dont cares only express flexibility for a single output 7

Terminology 8

Problem Definition 9 Implement dual-node Boolean relation- based multi-level logic minimization technique Goals: Method must scale to large designs Compare to best dont care-based method (single-node)

Previous Work 10 [CM77] Formulated multi-node minimization problem No results provided [WW94] Multi-node minimization Extremely large runtimes, works on very small designs [MB05] Single node approach, uses windowing and SAT based formulation Used for comparison purposes This work: Efficient choice of nodes, window based, efficient quantification scheduling

Approach Key features Dual node optimization Careful node pair selection Window based optimization technique Early quantification for efficiency 11

Approach 12

Node Pair Selection 13

Node Pair Selection 14

Node Pair Selection 15

Node Pair Selection Compute common input ratio Compute common output ratio Select node pairs that satisfy 16

Subnetwork Extraction 17

Subnetwork Extraction 18

Building the Relation where 19

Quantification Scheduling 20

Quantification Scheduling 21

Quantification Scheduling 22

Call BREL (a Boolean relation minimizer) to minimize Returns new nodes and Graft new nodes into Delete original nodes, Endgame 23

BREL 24 BREL is a heuristic Boolean relation solver Solving a Boolean relation Same as minimum cost determinization of the relation (i.e. finding the lowest cost function which is contained in the relation) Branch and bound approach

Experimental Results Implemented in SIS Uses CUDD ROBDD Package 15 benchmark circuits from mcnc91, itc99 Metric for quality: literal count Preprocessing steps: Removes constant-valued nodes Removes nodes that do not fanout Merges functionally identical nodes 25

Experimental Results Parameter selection 4 parameters to node selection algorithm Goal: Find golden values 26

Experimental Results Parameter: 27

Experimental Results Parameters: : Window size : Partners for 28

Experimental Results 29

Experimental Results Parameter: 30

Experimental Results Golden parameter values: Can be modified to balance quality/runtime 31

Experimental Results Compared versus 12% lit. improvement 38x runtime increase But runtimes are still within 3-4 min Low memory (#BDD nodes) High gain (number of node pairs which give an improvement) 32

Experimental Results Run after 13% lit. improvement Both use 2x2 windows 33

Experimental Results Limit subnetwork size τ 34

Conclusions 12% less literals than best DC approach Runtimes under 4 minutes for largest network Low memory usage Further reduce literals by 13% after running best DC approach Future Work Consider 3+ nodes in relation SAT-based relation construction Alternative to BREL 35

36 Thank you!

37 SAT-Sweep

38 BREL

39 BREL