ITC 2016 PO 16: Testing Yield Improvement by Optimizing the Impedance of Power Delivery Network on DIB Jintao Shi Zaiman Chen.

Slides:



Advertisements
Similar presentations
RL-RC Circuits & Applications SVES Circuits Theory
Advertisements

[ 1 ] LVDS links Servizio Elettronico Laboratori Frascati INFN - Laboratori Nazionali di Frascati G. Felici LVDS links.
Design and Application of Power Optimized High-Speed CMOS Frequency Dividers.
® WPD WORKSTATION PRODUCTS DIVISION 1 Page 1 IEEE EPEP2000 Via and Return Path Discontinuity Impact on High Speed Digital Signal Qinglun Chen, Intel WPD.
Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal
Plasma E- Measurement Brian DeHerrera John Purcell Jaber Assiri.
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.
Priyadharshini Shanmugasundaram Vishwani D. Agrawal DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING.
Foundations of Physics
Chapter 6 Voltage Regulators - Part 1- VOLTAGE REGULATION Two basic categories of voltage regulation are:  line regulation;  load regulation. line.
2.4GHz Single Balanced Mixer Andrew Bacon Jacqueline Griffin John Stone.
The new E-port interface circuits Filip Tavernier CERN.
Alternating-Current Circuits Chapter 22. Section 22.2 AC Circuit Notation.
Alternating Current Circuits
Copyright © 2009 Pearson Education, Inc. Chapter 30 Inductance, Electromagnetic Oscillations, and AC Circuits.
1 Wireless power for mobile phones - System overview Nov 25, 2012 V1.1.
Electrical Principles 1 1 G5 - ELECTRICAL PRINCIPLES [3 exam questions - 3 groups] G5A - Reactance; inductance; capacitance; impedance; impedance matching.
Electrical Resistance and Ohm’s Law Electric circuits are used to convert electrical energy into some other form of energy we need.
Operational Amplifiers AC Power CHAPTER 8. Figure 8.2, A voltage amplifier Figure 8.2 Simple voltage amplifier model Figure 8.3.
Copyright © 2012 Pearson Education Inc. PowerPoint ® Lectures for University Physics, Thirteenth Edition – Hugh D. Young and Roger A. Freedman Lectures.
MICAS Department of Electrical Engineering (ESAT) AID–EMC: Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene Update of the “Digital EMC project”
Operational Amplifiers and Other Integrated Circuit Usage Jimmie Fouts Houston County Career Academy.
Design of Digital-to-Analog Converter Qin Chen Yong Wang Dept. of Electrical Engineering Mar. 14th, 2006 EE597G Presentation:
Copyright © 2009 Pearson Education, Inc. Chapter 33 Inductance, Electromagnetic Oscillations, and AC Circuits Part II.
An accurate and efficient SSO/SSN simulation methodology for 45 nm LPDDR I/O interface Dr. Souvik Mukherjee, Dr. Rajen Murugan (Texas Instruments Inc.)
RC Circuits Chapter 10 Thomas L. Floyd David M. Buchla DC/AC Fundamentals: A Systems Approach.
Distributed Computation: Circuit Simulation CK Cheng UC San Diego
Non - Inverting Amplifier
Class Discussion 2.2 Improper Application of a Voltage Divider Kyle I. Platt Mechatronic Systems EAS 5407.
CONTENTS: 1.Abstract. 2.Objective. 3.Block diagram. 4.Methodology. 5.Advantages and Disadvantages. 6.Applications. 7.Conclusion.
Electrical Principles 1 1 G5 - ELECTRICAL PRINCIPLES [3 exam questions - 3 groups] G5A - Reactance; inductance; capacitance; impedance; impedance matching.
CSE598A Analog Mixed Signal CMOS Chip Design FM Mixer CMOS Realization (Final Presentation) Zhang Yi.
ELECTROMOTIVE FORCE. Consider the following diagram showing a circuit with an external resistance (R) internal resistance (r) and EMF ( ε ). When.
M. Atef, Hong Chen, and H. Zimmermann Vienna University of Technology
Unit 7, Chapter 20 CPO Science Foundations of Physics.
Visible Light Photon Counter Integrator Group 48: Katie Nguyen, Austin Jin ECE445 Spring 2016 May 1, 2016.
Design and Development of Transient Network Analyzer By M.Satish kumar 04131A0241 P.Sasi kumar 04131A0240 T.Sirisha 04131A0244 V.S.Pramod 04131A0247 Under.
High Gain Transimpedance Amplifier with Current Mirror Load By: Mohamed Atef Electrical Engineering Department Assiut University Assiut, Egypt.
Exploring the Rogue Wave Phenomenon in 3D Power Distribution Networks Xiang Hu 1, Peng Du 2, Chung-Kuan Cheng 2 1 ECE Dept., 2 CSE Dept. University of.
STT-RAM Feasibility Study Amr Amin UCLA Jan 2010.
MICROPROCESSOR DESIGN1 IR/Inductive Drop Introduction One component of every chip is the network of wires used to distribute power from the input power.
High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology
Chapter 31 Alternating Current.
Determining Equivalent Resistance
AIDA design review 31 July 2008 Davide Braga Steve Thomas
Day 38: December 4, 2013 Transmission Lines Implications
WEBENCH® Coil Designer
THE CMOS INVERTER.
Chapter 17 Resonance Circuits.
Inductance, Electromagnetic Oscillations, and AC Circuits
Lets Design an LNA! Anurag Nigam.
CSE598A Analog Mixed Signal CMOS Chip Design
Textbook Detection System With Radio-Frequency Identification
MECH 373 Instrumentation and Measurements
Harmonic Distortion Analyzer, Wave Analyzer and Function Generator
DCH preamplifier developments In Montreal
Series and Parallel Circuits
Low Power and High Speed Multi Threshold Voltage Interface Circuits
Industrial Electronics
Series and Parallel Circuits
Chapter 31 Electromagnetic Oscillations and Alternating Current
Circuit Design Techniques for Low Power DSPs
Load-Pull Measurements
Electric Circuits Fundamentals
A 24 GHz Low Noise Amplifier: Design, Construction, and Testing
Energy Efficient Power Distribution on Many-Core SoC
Alternating Current Circuits
Invisible Connections Will Unveil Our 5G Future
Presentation transcript:

ITC 2016 PO 16: Testing Yield Improvement by Optimizing the Impedance of Power Delivery Network on DIB Jintao Shi Zaiman Chen and Yu Huang Peilai Zhang Figure 4: X-axis: Time, Y-axis: Power (Current / Toggle Rate). Use it to calculate the threshold impedance – 20uO – 30uO (Micro Ohm) Figure 3: X-axis: Frequency, Y-axis: Impedance Figure Shmoo: X-axis: Voltage, Y-axis: Frequency Signal output input to the force point, signal input is measure at the sense point Scan Test Challenges Caused by IR Drop Shmoo of the Same Device on 8 Different Sites Transition delay at-speed tests are sensitive to IR drops on the power supplies Impedances of Power Delivery Network (PDN) on Device Interface Board (DIB) have big impact on the IR drop In multi-site testing, different sites may have different PDN impedances vs. frequencies due to variations of layout traces or capacitance values Multi-site testing may introduce even larger yield loss due to variations of IR drops on PDNs Proposed Flow Step 1: Analyze Step 1. Analyze test power to identify sensitive frequencies and calculate the impedance thresholds at these points Identify the sensitive frequency points, at which the worst IR drops may happen. The following is an example of peak power analysis results based on simulation. Step 2. Measure how PDN impedances vary with frequencies at different test sites Step 3. Optimize the PDN impedance if it is over the threshold Step 2: Measure A circuit is developed to scan the PDN impedance on each site. Its block diagram is illustrated as follows With the designed circuitry, we measure the impedance vs. the frequency. In this example, the best sites are Sites 6 and 7 and the worst sites are Sites 0 and 3, which matched the shmoo results Step 3: Optimize If at some sensitive frequencies, the measured impedance is larger than the calculated threshold, we will tune the capacitances on the PDN such that its impedance will drop to a safe level and IR drop will not likely occur. This can minimize yield loss due to IR drops.