* * * * * * * 8051 Interrupts Programming

8051 Interrupts An interrupt is the occurrence of a condition – an event - which interrupts normal program flow Interrupts allow a system to respond to asynchronous events (not in program flow) and handle the events while another task is running An interrupt driven system gives the illusion of doing many things simultaneously (multitasking on one CPU) The routine that deal’s with a specific interrupt is called an Interrupt Service Routine (ISR) or an “interrupt handler” Interrupts routines are activated by the occurrence of either an external or an internal event (a.k.a. exceptions) Interrupt routines are said to run in the “background” while the main system program runs in the “foreground”

Interrupt Service Interrupts allow the 8051 to respond to asynchronous events (external or internal) only when required. The alternative is called “polling” – testing status bits - which can be time consuming, wasting precious CPU resources/cycles Interrupts introduce the concept of “priority” where one interrupt is given preference over another simultaneous interrupt Interrupt Vectors--where is the address of the ISR when a particular interrupt occurs? only when interrupts are enabled 8051 Interrupt Vector Table (Atmel 89C51RD2 has 3 more – not covered) Interrupt Vector Address Number Bytes Pin Flag Clearing Comment Reset 0000H 3 Auto Power-on INT0 0003H 8 P3.2 External Hardware TF0 000BH Timer 0 INT1 0013H P3.3 TF1 001BH Timer 1 RI/TI 0023H Programmer Serial Communication TF2/EXF2 002Bh Timer 2 Each has 2 possible reasons for interrupt

Interrupt Service Sequence When an interrupt is activated the 8051… Finishes the instruction currently being executed Saves the current status of all the interrupts and stores the current PC  Stack Vectors (i.e. jumps) to the corresponding location within the interrupt vector table, i.e. PC  Vector Table address Option 1: If the ISR fits in the available space you can immediately service the interrupt Option 2: If the ISR is too large then the vector table contains a long jump (ljmp) to the Interrupt Service Routing (ISR) The last instruction of the ISR is a “reti” (Return from Interrupt) Responsibility of ISR to save/restore any registers that it uses, including the PSW, having the same number of pushes and pops to/from the stack for the “reti” instruction to work correctly Original PC is popped off the stack – returning to where program was when the interrupt occurred

Enabling/Disabling Interrupts All interrupts are disabled (masked) at system reset Software enables those interrupts required IE (A8h) Interrupt Enable SFR is used to enable/disable interrupts EA -- ET2 ES ET1 EX1 ET0 EX0 7 6 5 4 3 2 1 0 EA IE.7 Global enable. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit - IE.6 Not implemented. Don’t set. ET2 IE.5 Enables/disables Timer 2 TF2 or EXF2 interrupt (8052) ES IE.4 Enables/disables Serial Port RI or TI interrupt ET1 IE.3 Enables/disables Timer 1 overflow interrupt EX1 IE.2 Enables/disables External interrupt 1 ET0 IE.1 Enables/disables Timer 0 overflow interrupt EX0 IE.0 Enables/disables External interrupt 0

Interrupt Priority Levels Each interrupt source is individually programmed as being a “high” or “low” priority interrupt Prioritized allows resolution of simultaneous interrupts Prioritized interrupts allow for “preemptive” interrupt handlers IP (B8h) – Interrupt Priority SFR Priority is either high (1) or low (0) If an ISR is active and a higher priority interrupt occurs, it is interrupted (i.e. preempted). A high level ISR can not be interrupted. -- IP.7 Undefined -- IP.6 Undefined PT2 IP.5 Priority for Timer 2 interrupt PS IP.4 Priority for serial port interrupt PT1 IP.3 Priority for Timer 1 interrupt PX1 IP.2 Priority for external 1 interrupt PT0 IP.1 Priority for Timer 0 interrupt PX0 IP.0 Priority for external 0 interrupt

Interrupt Priority Levels (enhanced) Each interrupt source is individually programmed to one of four priority levels (00, 01, 10, 11) IPH (B7h) – Interrupt Priority HIGH IPL (B8h) – Interrupt Priority LOW Priority from highest to lowest (3,2,1,0) If an ISR is active and a higher priority interrupt occurs, it is interrupted. A higher level ISR can not be interrupted. Equal priorities yield to polling sequence (cf. page 75, AT8951RD2 spec) -- IP (H/L). 7 Undefined -- IP (H/L). 6 PCA (Programmable Counter Array) PT2 IP (H/L). 5 Priority for Timer 2 interrupt PS IP (H/L). 4 Priority for serial port interrupt PT1 IP (H/L). 3 Priority for Timer 1 interrupt PX1 IP (H/L). 2 Priority for external 1 interrupt PT0 IP (H/L). 1 Priority for Timer 0 interrupt PX0 IP (H/L). 0 Priority for external 0 interrupt

External Interrupts 8051 has two external interrupts: INT0 and INT1 Tied to external pins: INT0 (P3.2), INT1 (P3.3) P3.2 and P3.3 are general purpose I/O pins until the respective Interrupt Enable bits are set (i.e. EX0 and EX1, respectively) Activation of external interrupts 8051 external interrupts activated in one of two ways (1) Level-triggered of (2) edge-triggered TCON.0 (IT0) and TCON.2 (IT1) defines “interrupt type“ IT0/IT1 = 0 for level-triggered interrupts (default) IT0/IT1 = 1 for edge triggered interrupts INT1 Vcc 8051 Pull-up IE1 IT1 TCON (88h) 7 6 5 4 3 2 1 0 IE0 IT0 TF1 TR1 TF0 TR0

External Interrupts (cont.) Level-triggered interrupts INT0/INT1 held normally HIGH. A LOW level on one of these signals will trigger the respective interrupt The 8051 keeps sampling INTn for a LOW once each machine cycle Some 8051’s specify that “the pin must be held in a LOW state until the start of the execution of the ISR. If the INTn pin is brought back to a HIGH before the start of the ISR, there will be no interrupt.” Thus, to ensure activation of an external interrupt, it must remain LOW for at least 4 machine cycles The LOW on the pin must be removed before the last instruction in the ISR (reti) is executed else another interrupt will occur

External Interrupts (cont.) Edge-triggered interrupts Setting IT1 or IT0 to “1” programs the 8051 to detect edge-triggered signals INT1/INT0 held normally HIGH. A HIGH-to-LOW transition on one of these signals will trigger the respective interrupt In edge-triggered interrupts, the INT1/INT0 signal must be held HIGH for at least one machine cycle, and then held LOW for at least one machine cycle to ensure that the transition is “seen” by the 8051 The 8051 automatically sets the respective “External Interrupt Edge Flag” (IE1/IE0) in the TCON register when using edge-trigerring Regarding the “Interrupt Type” bits (IT1/IT0) in the TCON register, the following two points must be emphasized: Upon execution of a “RETI” instruction, the respective IEn bit will be cleared automatically, indicating the edge-triggered interrupt has been serviced While the ISR is being executed, the 8051 ignores all transitions on the external interrupt signals INT1/INT0 IE1 IT1 TCON (88h) 7 6 5 4 3 2 1 0 IE0 IT0 TF1 TR1 TF0 TR0

Review of Timer Control register - TCON TCON (88h) Bit Symbol Comment TCON.7 TF1 T1 Overflow Flag TCON.6 TR1 T1 Run Control (1=ON, 0=OFF) TCON.5 TF0 T0 Overflow Flag TCON.4 TR0 T1 Run Control (1=ON, 0=OFF) TCON.3 IE1 EI1 edge flag. SET on H2L transition. Cleared by CPU TCON.2 IT1 I1 type control. 1=falling edge,0=low-level activated TCON.1 IE0 EI0 edge flag. SET on H2L transition. Cleared by CPU TCON.0 IT0 I0 type control. 1=falling edge,0=low-level activated Edge-detect: the input must be held HIGH for one cycle and LOW for another. IE0/IE1 automatically cleared when CPU vectors to interrupt Level-activated: the input must be held until interrupt generated. Must also be de-activated before the ISR is completed. Usually the ISR “acknowledges” the interrupt and the interrupting device removes the interrupt request External Interrupts are sampled once each machine cycle so input should be held for at least 12 oscillator periods to ensure proper sampling

Programming the Serial Comm. Interrupt TI (Transmit Interrupt) is set when the last bit of framed data, the stop bit, is transmitted – indicating that SBUF is empty and ready for another byte RI (Receive Interrupt) is set when an entire frame of data is correctly received indicating that SBUF now has a byte ready to be read Behavior of TI and RI is the same whether we are polling or using interrupts. Difference is how we detect and respond to its occurrence TI and RI are OR’d to generate a single interrupt User must determine which is the source in the ISR Typical use relies on RI for data received but will poll TI to ensure data sent Analogous to receiving and generating a phone call Always clear TI or RI prior to execution of reti