Design Flow System Level Πανεπιστήμιο Θεσσαλίας ΤΜΗΜΑ ΜΗΧΑΝΙΚΩΝ ΗΛΕΚΤΡΟΝΙΚΩΝ ΥΠΟΛΟΓΙΣΤΩΝ, ΤΗΛΕΠΙΚΟΙΝΩΝΙΩΝ ΚΑΙ ΔΙΚΤΥΩΝ Τομέας Υλικού και Αρχιτεκτονικής Υπολογιστών ΗΥ532 – Microprocessor Design Design Flow System Level

Electronic System Design 6-Νου-18

Top-Down Design The top-level system is modeled for functionality and performance using a high level behavioral description. Each major component is modeled at the behavioral level and the design is simulated again for functionality and performance. Each major component is modeled at the gate level and the design is simulated again for timing, functionality and performance. 6-Νου-18

Levels of Abstraction : Capture 6-Νου-18

Levels of Abstraction : Definition 6-Νου-18

Tradeoffs Between Abstraction Levels 6-Νου-18

System Level Modeling VHDL Behavioral SystemC/SystemVerilog 6-Νου-18

VHDL Behavioral Behavioral Description Describe the functionality of your design to Behavioral Compiler,using a behavioral level of abstraction. This behavioral description details when the inputs are read,what Operations are to be performed on the input data, and when the results of the processing are to be written to the output ports. The Behavioral Compiler tool synthesizes a VHDL behavioral hardware description, written at a behavioral level of abstraction, Into an RTL or a gate-level netlist. 6-Νου-18

SystemC : C/C++ out of the box C/C++ does not support Hardware style communication Signals, events, …etc. Notion of time Time sequenced operations Concurrency Hardware and systems are inherently concurrent, ie components operate in parallel Reactivity HW is inherently reactive, it responds to stimuli and is in constant interaction with its environment, which requires handling of exceptions Hardware datatypes Bit type, bit-vector type, multi-valued logic type, signed and unsigned integer types and fixed-point types 6-Νου-18

What is SystemC? ... A language extension to C/C++ to describe and simulate HW/SW systems: Multiple levels of abstraction Concurrency IP reuse methodology SystemC Library ... A C++ class library to standardize C-based system modelling ... A basic simulation kernel 6-Νου-18

System Design Flow & Abstraction Levels 6-Νου-18

Architectural Level In a typical top-down design flow, you start with a purely functional model of your system. This functional model is a software program that describes the system functionality so that it can be validated. This functional model is then mapped into a system architectural model. In addition to the system functionality, the system architectural model describes its architecture(buses, memory, processors, peripherals, and so forth). 6-Νου-18

Behavioral Model A behavioral model of a block in a system is an algorithmic description of the block’s behavior. Unlike a pure software program, however, the I/O behavior of the block is described in a cycle-accurate fashion. Therefore, wait statements are inserted into the algorithmic description to clearly delineate clock-cycle boundaries and when I/O happens. Unlike register transfer level (RTL) descriptions, the behavior of the block is still described algorithmically rather than in terms of a finite state machine (FSM) and a data path. Therefore, behavioral descriptions are more compact and easier to understand, and because of the higher level of abstraction, they simulate faster than RTL. 6-Νου-18

Register Transfer Level Model An RTL model describes registers in your design and the combinational logic between the registers. As such, the functionality of your system is specified as an FSM and a data path. Because register updates are tied to a clock, the model is cycle-accurate, both at the interfaces and also internally. Internal cycle accuracy means that the clock cycle in which each operation is performed is specified. This is different from a behavioral model that is cycle-accurate at the interface. 6-Νου-18

SystemC Example 6-Νου-18 // system top level and netlist main.cpp #include “systemc.h” #include “adder.h” #include “stimgen.h” #include “monitor.h” int sc_main(int argc, char *argv[] ) { // Create fifos channels with a depth of 10 sc_fifo<int> s1(10); sc_fifo<int> s2(10); sc_fifo<int> s3(10); // Module instantiations // Stimulus generator stimgen stim(“stim”); stim(s1,s2); // Adder adder add(“add”); add(s1, s2, s3); // Response monitor monitor mon(“mon”); mon.re(s3); // Start simulation sc_start(); return 0; } Stimulus Generator s1 Adder Response Monitor a1 in1 s3 out re s2 a2 in2 // Header file adder.h SC_MODULE(adder) { //Input ports sc_port<sc_fifo_in_if<int> > in1; sc_port<sc_fifo_in_if<int> > in2; //Ouput ports sc_port<sc_fifo_out_if<int> > out; //sync process for adder void adder_proc(); //Module constructor SC_CTOR(adder){ SC_THREAD(adder_proc); } } // End of SC_MODULE(adder) // Implementation file adder.cpp #include “systemc.h” #include “adder.h” void adder::adder_proc() { while(true) { out->write(in1->read() + in2->read() ); out->write(in1->read() + in2->read() +2); } 6-Νου-18

System Level Power Modeling 6-Νου-18

Design Flow 6-Νου-18

Power Model and Tool Suite 6-Νου-18

Use cases ( I ) 6-Νου-18

Use cases ( II ) 6-Νου-18

Use cases ( III ) 6-Νου-18

Use cases (IV) 6-Νου-18

Use cases (V) 6-Νου-18

Scheduling 6-Νου-18

Power Optimized Floorplan 6-Νου-18