Formally capturing the structure of bus specifications

Slides:

Advertisements

Similar presentations

1 IP-Based System-on-Chip Design 2002 IP Reuse Hardening via Embedded Sugar Assertions Erich Marschner 1, Bernard Deadman 2, Grant Martin 1 1 Cadence Design.

Advertisements

DATE 2003, Munich, Germany Formal Verification of a System-on-Chip Bus Protocol Abhik Roychoudhury Tulika Mitra S.R. Karri National University of Singapore.

Part 4: combinational devices

RISC and Pipelining Prof. Sin-Min Lee Department of Computer Science.

CSE 202 – Formal Languages and Automata Theory 1 REGULAR LANGUAGE.

CSE 201 Computer Logic Design * * * * * * * Verilog Modeling

Simplifying the Integration of Processing Elements in Computing Systems using a Programmable Controller By Lesley Shannon and Paul Chow University of Toronto.

© Chinese University, CSE Dept. Software Engineering / Software Engineering Topic 1: Software Engineering: A Preview Your Name: ____________________.

CSCE 211: Digital Logic Design. Chapter 6: Analysis of Sequential Systems.

Flip - flops. We begin our study of such circuits be discussing the elements necessary to implement the “storage” portion of sequential systems. I present.

1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 5: Memory and Peripheral Busses September 21, 2010.

1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 6: AHB-Lite, Interrupts (1) September 18, 2014 Slides developed.

Chapter 4: The Building Blocks: Binary Numbers, Boolean Logic, and Gates Invitation to Computer Science, Java Version, Third Edition.

Overview Finite State Machines - Sequential circuits with inputs and outputs State Diagrams - An abstraction tool to visualize and analyze sequential circuits.

Analog-to-Digital Converters

Embedded Systems Laboratory Department of Computer and Information Science Linköping University Sweden Formal Verification and Model Checking Traian Pop.

Department of Electrical Engineering and Computer Sciences University of California at Berkeley The Ptolemy II Framework for Visual Languages Xiaojun Liu.

Lesson-21Process Modeling Define systems modeling and differentiate between logical and physical system models. Define process modeling and explain its.

Department of Computer Science 1 CSS 496 Business Process Re-engineering for BS(CS)

Department of Computer Science 1 CSS 496 Business Process Re-engineering for BS(CS)

Presenter : Cheng-Ta Wu Vijay D’silva, S. Ramesh Indian Institute of Technology Bombay Arcot Sowmya University of New South Wales, Sydney.

1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 5: Memory and Peripheral Busses September 20, 2011.

CS 360 Lecture 6.  A model is a simplification of reality  We build models to better understand the system being developed.  We build models of complex.

On Chip Bus National Taiwan University

CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur

Computer Architecture System Interface Units Iolanthe II approaches Coromandel Harbour.

SESSION 2.1 PROGRAMME OF ASSESSMENT TASKS IN GET GRADES R-9.

1 Control Unit Operation and Microprogramming Chap 16 & 17 of CO&A Dr. Farag.

SOC Consortium Course Material On Chip Bus National Taiwan University Adopted from National Taiwan University SOC Course Material.

1 EECS 373 Design of Microprocessor-Based Systems Mark Brehob University of Michigan Lecture 12: Memory and Peripheral Busses October 22nd, 2013 Slides.

ECE-C662 Lecture 2 Prawat Nagvajara

Hamming Code,Decoders and D,T-flip flops Prof. Sin-Min Lee Department of Computer Science.

Differences and distinctions: metadata types and their uses Stephen Winch Information Architecture Officer, SLIC.

CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur

CSE 202 – Formal Languages and Automata Theory 1 REGULAR EXPRESSION.

System modeling and the Unified Modeling Language (UML) CS

General Discussion of “Properties” The Pumping Lemma Membership, Emptiness, Etc.

Slides developed in part by Mark Brehob & Prabal Dutta

ATLAS Pre-Production ROD Status SCT Version

Class Exercise 1B.

Overview Register Transfer Language Register Transfer

ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.

Invitation to Computer Science, Java Version, Third Edition

CS/COE0447 Computer Organization & Assembly Language

Computer Organization and Design

COSC 2021: Computer Organization Instructor: Dr. Amir Asif

ME2100 EMBEDDED SYSTEM DESIGN (ARM9™) [Slide 8] ARM AMBA Bus BY DREAMCATCHER

Gabor Madl Ph.D. Candidate, UC Irvine Advisor: Nikil Dutt

Formal Performance Evaluation of AMBA-based System-on-Chip Designs

Sequential Circuits Constructive Computer Architecture Arvind

Burst read Valid high until ready high

Unified Modeling Language

SOC Design Lecture 4 Bus and AMBA Introduction.

ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch

INFS 6225 Object Oriented Systems Analysis & Design

HDL Hardware Description Language

The Processor Lecture 3.2: Building a Datapath with Control

The design, implementation, integration and evaluation of a Statechart service. By Xin Bai Feb 7, 2002.

Error Detection / Correction

De-synchronization: from synchronous to asynchronous

Lecture 6 CdM-8 CPU overview

Computer Organization and Assembly Languages Yung-Yu Chuang 2005/09/29

Levels in Processor Design

Analyze, compare, create, and compose shapes

Chapter 13: I/O Systems.

Computer Architecture Assembly Language

Lecture 4 Sequential units. Registers

EECS 373 Design of Microprocessor-Based Systems Prabal Dutta

Real-Time Systems, COSC , Lecture 18

Presentation transcript:

Formally capturing the structure of bus specifications Kathi Fisler WPI Computer Science

Basic transfer Burst operation

First two diagrams should compose to yield third Glitches … and lack thereof Periods of instability

Compositional Core Protocols HADDR HWRITE HWDATA HREADY = Addr = H = dc ; dc* ; Data ; dc* ; H ; dc* Different cycle lengths per concatenation

Compositional Core Protocols HADDR HWRITE HWDATA HREADY = Addr = H = dc ; dc* ; Data ; dc* ; H ; dc* Core diagram abstracts part of protocol

Compositional Core Protocols HADDR HWRITE HWDATA HREADY = Addr = H = dc ; dc* ; Data ; dc* ; H ; dc* single logical value Diagrams in document show implementation, not specification

Compositional Core Protocols HADDR HWRITE HWDATA HREADY = Addr = H = dc ; dc* ; Data ; dc* single logical value Must decouple clocking and concatenation Two-dimensional regular expression

Naïve regular expressions elide causality and control Events trigger diagram blocks Exploring functional reactive languages (eg FrTime)

Each portion builds on earlier protocols and adds complexity Basic transfer How do we design a specification language to capture this structure? Burst operation Error conditions Split transfers Reset transfers