Day 6: September 11, 2013 Restoration ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 6: September 11, 2013 Restoration Penn ESE370 Fall2013 -- DeHon

Today How do we make sure logic is robust Can assemble into any (feed forward) graph Can tolerate voltage drops and noise ….while maintaining digital abstraction Penn ESE370 Fall2013 -- DeHon

Outline Two problems Cascade failure Restoration Transfer Curves Noise Margins Non-linear Penn ESE370 Fall2013 -- DeHon

Two Problems Output not go to rail Signals may be perturbed by noise Stops short of Vdd or Gnd Signals may be perturbed by noise Vx = Videal ± Vnoise Penn ESE370 Fall2013 -- DeHon

Wire Resistance Last Wednesday: Rwire=10Ω Penn ESE370 Fall2013 -- DeHon

Wire Resistance 1000 mm long wire? 1 cm long wire? Length of integrated circuit chip side? (we often call an IC chip a “die”) Penn ESE370 Fall2013 -- DeHon

Die Sizes Processor Die Size Transistor Count Process Core 2 Extreme X6800 143 mm² 291 Mio. 65 nm Core 2 Duo E6700 143 mm² 291 Mio. 65 nm Core 2 Duo E6600 143 mm² 291 Mio. 65 nm Core 2 Duo E6400 111 mm² 167 Mio. 65 nm Core 2 Duo E6300 111 mm² 167 Mio. 65 nm Pentium D 900 280 mm² 376 Mio. 65 nm Athlon 64 FX-62 230 mm² 227 Mio. 90 nm Athlon 64 5000+ 183 mm² 154 Mio. 90 nm http://www.tomshardware.com/reviews/core2-duo-knocks-athlon-64,1282-4.html Penn ESE370 Fall2013 -- DeHon

Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall2013 -- DeHon

Implications What does the circuit really look like for an inverter in the middle of the chip? Rwire Rrest_of_chip Penn ESE370 Fall2013 -- DeHon

Rrest_of_chip IR-Drop Since interconnect is resistive and gates pull current off the supply interconnect The Vdd seen by a gate is lower than the supply Voltage by Vdrop=Isupply x Rdistribute Two gates in different locations See different Rdistribute Therefore, see different Vdrop Penn ESE370 Fall2013 -- DeHon

Output not go to Rail CMOS, capacitive load  no problem CMOS, resistive load  voltage divider Due to IR drop, “rails” for two communicating gates may not match Penn ESE370 Fall2013 -- DeHon

Two Problems Output not go to rail Signals may be perturbed by noise Is this tolerable? Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage Penn ESE370 Fall2013 -- DeHon

Noise Sources? What did we see in lab when zoomed in on signal transition? Signal coupling Crosstalk Leakage Ionizing particles IR-drop in signal wiring Penn ESE370 Fall2013 -- DeHon

Signals will be degraded Output not go to rail Is this tolerable? Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage What happens to degraded signals? Penn ESE370 Fall2013 -- DeHon

Preclass All 1’s  logical output? Penn ESE370 Fall2013 -- DeHon

Preclass 1.0 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2013 -- DeHon

Preclass 0.95 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2013 -- DeHon

Degradation Cannot have signal degrade across gates Want to be able to cascade arbitrary set of gates Penn ESE370 Fall2013 -- DeHon

Gate Creed Gates should leave the signal “better” than they found it “better”  closer to the rails Penn ESE370 Fall2013 -- DeHon

Restoration Discipline Define legal inputs Gate works if Vin “close enough” to the rail Restoration Gate produces Vout “closer to rail” This tolerates some drop between one gate and text (between out and in) Call this our “Noise Margin” Penn ESE370 Fall2013 -- DeHon

Noise Margin Voh – output high Vol – output low Vih – input high Vil – input low NMh = Voh-Vih NMl = Vil-Vol One mechanism, addresses numerous noise sources. Penn ESE370 Fall2013 -- DeHon

Restoration Discipline (getting precise) Define legal inputs Gate works if Vin “close enough” to the rail Vin > Vih or Vin < Vil Restoration Gate produces Vout “closer to rail” Vout < Vol or Vout > Voh Note: don’t just say Vin>Vih  Vout>Voh Penn ESE370 Fall2013 -- DeHon

Transfer Function What gate is this? Penn ESE370 Fall2013 -- DeHon

Restoring Transfer Function Penn ESE370 Fall2013 -- DeHon

Decomposing What is gain? Where is there gain? |DVout/Dvin| > 1 Where is there gain? Where is there not gain? Dividing point? Penn ESE370 Fall2013 -- DeHon

Restoring Transfer Function Vil, Vih = slope -1 points Voh =f(Vil) Vol=f(Vih) Penn ESE370 Fall2013 -- DeHon

Restoring Transfer Function Vil, Vih = slope -1 points Voh =f(Vil) Vol=f(Vih) Closer to rail than Vil, Vih Not make much difference on Vout Making Vil lower would reduce NM = Vil-Vol Penn ESE370 Fall2013 -- DeHon

Controlling Value Consider a nor2 gate If want one input to control the output What value should the other input be? We call this input the non-controlling input since it does not determine the output What should the non-controlling input value be for a nand2 gate? Penn ESE370 Fall2013 -- DeHon

Restoring Transfer Function For multi-input functions, should be worst case. i.e. hold non-controlling inputs at Vil, Vih respectively. (relate preclass exercise) Penn ESE370 Fall2013 -- DeHon

Ideal Transfer Function Penn ESE370 Fall2013 -- DeHon

Linear Transfer Function? O=Vdd-A Noise Margin? Penn ESE370 Fall2013 -- DeHon

Linear Transfer Function? Consider two in a row (buffer) O1=Vdd-A What is transfer function to buffer output O2? O2=(Vdd-O1) = Vdd-(Vdd-A)=A Penn ESE370 Fall2013 -- DeHon

Linear Transfer Function? For buffer: O2=A Consider chain of buffers What happens if A drops a bit between each buffer? Ai+1 = Ai-Δ Conclude: Linear transfer functions do not provide restoration. Penn ESE370 Fall2013 -- DeHon

Non-linearity Need non-linearity in transfer function Could not have built restoring gates with R, L, C circuit Linear elements Penn ESE370 Fall2013 -- DeHon

Transistor Non-Linearity Penn ESE370 Fall2013 -- DeHon

All Gates If we hope to assemble design from collection of gates, Voltage levels must be consistent and supported across all gates Must adhere to a Vil, Vih, Vol, Voh that is valid across entire gate set Penn ESE370 Fall2013 -- DeHon

Big Idea Need robust logic Restoration and noise margins Can assemble into any (feed forward) graph Can tolerate loss and noise ….while maintaining digital abstraction Restoration and noise margins Every gate makes signal “better” Design level of noise tolerance Penn ESE370 Fall2013 -- DeHon

Admin HW2 due Thursday (tomorrow) Friday in Ketterer Monday back here Noise margin problem Friday in Ketterer Read through HW3 Transfer library/schematics to eniac Be ready to run electric and spice on linux CETS machines <or> own laptop that you bring with you Monday back here Penn ESE370 Fall2013 -- DeHon