Double Patterning-Aware Extraction and Static Timing Analysis Flows For Digital Design Sign-Off in 20/14nm Tamer Ragheb, Steven Chan, Adrian Au Yeung,

Slides:



Advertisements
Similar presentations
Energy stored in Magnetic Fields
Advertisements

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.
Tunable Sensors for Process-Aware Voltage Scaling
-1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon.
Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.
Logistics Network Configuration
1 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea MAPLD 148:"Is Scaling the Correct Approach for Radiation Hardened Conversions.
Variance reduction techniques. 2 Introduction Simulation models should be coded such that they are efficient. Efficiency in terms of programming ensures.
Parameterized Timing Analysis with General Delay Models and Arbitrary Variation Sources Khaled R. Heloue and Farid N. Najm University of Toronto {khaled,
The Cost of Fixing Hold Time Violations in Sub-threshold Circuits Yanqing Zhang, Benton Calhoun University of Virginia Motivation and Background Power.
Rasit Onur Topaloglu University of California San Diego Computer Science and Engineering Department Ph.D. candidate “Location.
Tirgul 9 Amortized analysis Graph representation.
Power-Aware Placement
On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.
Toward Performance-Driven Reduction of the Cost of RET-Based Lithography Control Dennis Sylvester Jie Yang (Univ. of Michigan,
University of Toronto Pre-Layout Estimation of Individual Wire Lengths Srinivas Bodapati (Univ. of Illinois) Farid N. Najm (Univ. of Toronto)
A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools.
Design of Integrated-Circuit Interconnects with Accurate Modeling of Chemical-Mechanical Planarization Lei He, Andrew B. Kahng* #, Kingho Tam, Jinjun Xiong.
Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography Kwangok Jeong and Andrew B. Kahng VLSI CAD LABORATORY.
UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.
Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,
A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas.
Ch 8.1 Numerical Methods: The Euler or Tangent Line Method
Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera Kyoto University.
UC San Diego / VLSI CAD Laboratory Toward Quantifying the IC Design Value of Interconnect Technology Improvement Tuck-Boon Chan, Andrew B. Kahng, Jiajia.
Chapter 07 Electronic Analysis of CMOS Logic Gates
Kwangsoo Han, Andrew B. Kahng, Hyein Lee and Lutong Wang
A Power Grid Analysis and Verification Tool Based on a Statistical Prediction Engine M.K. Tsiampas, D. Bountas, P. Merakos, N.E. Evmorfopoulos, S. Bantas.
Process Variation Mohammad Sharifkhani. Reading Textbook, Chapter 6 A paper in the reference.
An accurate and efficient SSO/SSN simulation methodology for 45 nm LPDDR I/O interface Dr. Souvik Mukherjee, Dr. Rajen Murugan (Texas Instruments Inc.)
RFIC – Atlanta June 15-17, 2008 RMO1C-3 An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio Emanuel Cohen.
March 23 & 28, Csci 2111: Data and File Structures Week 10, Lectures 1 & 2 Hashing.
1 Blend Times in Stirred Tanks Reacting Flows - Lecture 9 Instructor: André Bakker © André Bakker (2006)
CSCI1600: Embedded and Real Time Software Lecture 33: Worst Case Execution Time Steven Reiss, Fall 2015.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #8. VLSI Components in CMOS Technology  Introduction  Resistor Design  Capacitor Design  Inductor Design 
Static Timing Analysis
Sunpyo Hong, Hyesoon Kim
Design For Manufacturability in Nanometer Era
-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B.
Errors due to process variations Deterministic error –Characterized a priori Over etching, vicinity effects, … –A priori unknown Gradient errors due to.
Unified Adaptivity Optimization of Clock and Logic Signals Shiyan Hu and Jiang Hu Dept of Electrical and Computer Engineering Texas A&M University.
Slide 1 SLIP 2004 Payman Zarkesh-Ha, Ken Doniger, William Loh, and Peter Bendix LSI Logic Corporation Interconnect Modeling Group February 14, 2004 Prediction.
Power-Optimal Pipelining in Deep Submicron Technology
Conclusions & Recommendations
Motivation Process & Design trends
THE CMOS INVERTER.
The Interconnect Delay Bottleneck.
An Unobtrusive Debugging Methodology for Actel AX and RTAX-S FPGAs
A High-Speed and High-Capacity Single-Chip Copper Crossbar
Top-level Schematics Digital Block Sign-off Digital Model of Chip
Subject Name: File Structures
Capacitance variation 3/ (%)
Revisiting and Bounding the Benefit From 3D Integration
Description and Analysis of Systems
An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization
CSCI1600: Embedded and Real Time Software
Timing Analysis 11/21/2018.
Errors due to process variations
Arithmetic Mean This represents the most probable value of the measured variable. The more readings you take, the more accurate result you will get.
Is Co-existence Possible?
Chapter 4b Statistical Static Timing Analysis: SSTA
Post-Silicon Calibration for Large-Volume Products
Fine-Tuning your plan and obtaining approval
Technology scaling Currently, technology scaling has a threefold objective: Reduce the gate delay by 30% (43% increase in frequency) Double the transistor.
Measuring the Gap between FPGAs and ASICs
Applications of GTX Y. Cao, X. Huang, A.B. Kahng, F. Koushanfar, H. Lu, S. Muddu, D. Stroobandt and D. Sylvester Abstract The GTX (GSRC Technology Extrapolation)
Advanced Logical Effort
Chapter 4C Statistical Static Timing Analysis: SSTA
Beyond Si MOSFETs Part IV.
CSCI1600: Embedded and Real Time Software
Presentation transcript:

Double Patterning-Aware Extraction and Static Timing Analysis Flows For Digital Design Sign-Off in 20/14nm Tamer Ragheb, Steven Chan, Adrian Au Yeung, and Richard Trihy Design Methodology CAD Team June 2-6, 2013

Outline Why Double Patterning (DPT)? DPT Mask Misalignment Modeling in Parasitic Extraction Different DPT Extraction Flows Parasitic Extraction/STA Analysis on P&R Design Blocks Recommended 20/14nm Extraction/STA Block-Level Sign-Off Flow November 8, 2018

Why Double Patterning (DPT)? 20nm needs 64nm BEOL min. Pitch for scaling Delay in readiness of next generation lithography (NGL) BEOL min. pitch = 2.λsource.k1 / NA λsource =193nm / NA=1.35 / k1 is the process coefficient =0.25 (difficult printability) Min. Pitch ~ 72nm with one mask  Solution: Double Patterning Technology DPT utilizes the existing lithography intelligently Most commonly adopted approach is a litho-etch, litho-etch (LELE) Pros: Achieves 64nm pitch needed / Relaxes k1 coeff (better and more reliable litho) Cons: Can’t guarantee 100% accuracy in overlaying the two masks There are other techniques for double patterning such as litho-freeze, litho-etch (LFLE) and self-aligned double patterning (SADP) LELE achieves the best compromise between cost, processing, and yield Decomposition Two Masks One Mask November 8, 2018

DPT Misalignment Modeling Techniques: Mask Shift Two common approaches for DPT misalignment modeling: Mask shift flow Actually shifts one mask with respect to the other mask in XY directions Pros: Accurate if the mask misalignment on silicon is known (value & direction) Cons: Requires coloring or decomposing the design Requires designer to specify exact mask shift amount and direction for each DPT layer Determining worst case impact on timing requires 2N different shifts extractions per RC corner, where N is the number of DPT layers Mask shift flow let the DPT-aware extraction tool process the layout to actually shift one mask relative to the other (accurate results) It requires a fully decomposed (colored) design which means extra steps and major changes in the flows as compared to 28nm flow It requires a lot of trials to find the worst case condition (2^N different shifts for each shift value, where N is the number of DPT levels) It requires more trials if one assumes different shift value on each level November 8, 2018

DPT Misalignment Modeling Techniques: DPT Corner Two common approaches for DPT misalignment modeling: DPT corner flow Models mask misalignment as change in dielectric constant (ER_VS_SI_SPACING) Pros: Bounds mask misalignment effect Supports both colorless (non-decomposed) and colored (decomposed) flows Requires almost no changes to existing sign-off flows Cons: Can be pessimistic with respect to a real mask shift (assume change in space on both sides) DPT corner flow represents an approximation of the electrical effects of real physical mask shift Increases dielectric constant to represent a shift towards the neighbour (smaller space) Decreases dielectric constant to represent a shift far from the neighbour (larger space) This table is characterized using Raphael Simulations on test structures. It provides a seamless transition for designers from 28nm flows to 20nm/14nm flows since it requires almost no change to existing sign-off flows November 8, 2018

Full or selective coloring Different DPT-aware Extraction Flows Full or selective coloring November 8, 2018

Outline Why Double Patterning (DPT)? DPT Mask Misalignment Modeling in Parasitic Extraction Different DPT Extraction Flows Parasitic Extraction/STA Analysis on P&R Design Blocks Recommended 20/14nm Extraction/STA Block-Level Sign-Off Flow November 8, 2018

DPT Extraction/STA of P&R Design Blocks SIMD multi-media engine from a high-frequency CPU core Std cell count ~150K / Freq > 1.25GHz / with > 85% std cell utilization Routing on M2-M7 (M1 is reserved for standard cells only) Three different BEOL stack options used 3Mx: 3 DPT levels (baseline for comparison) 3Mx_dense: 3 DPT levels but denser than 3Mx 6Mx: 6 DPT levels For each of the 3 BEOL variants, we ran 13 different Extraction/STA flows Analyzed change in capacitance distribution / overall impact on timing & Frequency Extraction Flow Corner/Shift Decomposition Colored_DPmax DPT corner DPmax Fully-decomposed Colorless_DPmax Non-decomposed Shifts 1-4 Mask shift 4 Typical shifts (±x, ±y) Shifts 5-8 4 Maximum shifts (±x, ±y) Colored_DPmin DPmin Colorless_DPmin No DPT modeling Traditional We needed to study DPT misalignment effect on real design like a SIMD engine from ARM Cortex A9 We used 3 different BEOL stacks to study the DPT effect on different routing density and different number of DPT levels We will compare mask shifts in different directions and different shift values to the DPT corners flow results in both colorless and colored flows And to make the analysis complete, we will compare the effect on capacitance and then on the timing of the design using STA analysis November 8, 2018

Findings from Capacitance distributions Direction of mask shift is NOT important Statistically, shift value is more important Shift direction is important for specific paths (2N different combination/shift value) Both colored and colorless DPT corners/flows have similar results DPT corners bound ALL shifts DPT effect increases by increasing routing density & #of DPT layers Max. Shifts From the statistical distribution of total capacitance change due to each mask shift or DPT corner (assuming No_Shift situation as the reference for the analysis), we found that: Shifts 1-4 are typical shift value in different directions. We represented them as one curve because all the curves were almost exactly the same. The same for shifts 5-8 with max. shift value. The direction of shift does not matter as much when one looks at the full design but it is important for specific path study as we will see in later slides The DPT effect increases by increasing the density similar to SI effects. However, increasing number of DPT levels increases the DPT effect dramatically. Both colored and colorless DPT corners give almost the same mean results but colorless flow gives wider variance since it is more pessimistic (applies DPT effects every where) DPT corners bound nicely almost all the shift situations Typical Shifts November 8, 2018

Findings from STA Results: WNS Using the freq change in the slowest path “IP Freq” Direction of mask shift is important when we study just one path in STA Both colored and colorless DPT corners have similar results (timing difference within noise) DPT corners bound most mask shifts (all Typical shifts & most Max. shifts) From the STA results of the timing of worst path only in each situation due to each mask shift or DPT corner (assuming No_Shift situation as the reference for the analysis), we found that: Since it is only one path, then direction can matter (compare shift7 vs shifts 5,6,8) The DPT effect increases dramatically by increasing number of DPT levels (>3X effect) Both colored and colorless DPT corners give almost the same results DPT corners bound nicely almost all the shift situations Worst Negative Slack Path November 8, 2018

DPT effect w/o SI-aware routing DPT effect w/ SI-aware routing SI-aware Routing & Hold Time analysis DPT effect decreases by applying SI-aware routing ~50% reduction in DPT effects All our results with SI-aware routing DPT effect on Hold time is minimal due to: Short data paths – not much DPT effect Clock skew induced race conditions possible But DPT effect on clock skew is very small Most clock routes are not on DPT layers Clock is routed with 2w/2s NDRs – less impact Stack DPT effect w/o SI-aware routing DPT effect w/ SI-aware routing 3Mx ~X% <0.5X% 3Mx_dense ~Y% <0.7Y% 6Mx ~Z% ~0.5Z% As we discussed before that DPT can be considered as SI (Signal Integrity effect), therefore using SI-aware routing can reduce the DPT misalignment effect by ~50% All previous analyses were setup timing, but studying Hold timing, we found that DPT effect is minimal due to the layout nature of clock routes and short data paths November 8, 2018

Outline Why Double Patterning (DPT)? DPT Mask Misalignment Modeling in Parasitic Extraction Different DPT Extraction Flows Parasitic Extraction/STA Analysis on P&R Design Blocks Recommended 20/14nm Extraction/STA Block-Level Sign-Off Flow November 8, 2018

Extraction Corners Recommendations 5 traditional corners with mask_shift enabled Cmax / Cmin / Nominal / RCmax / RCmin Enable mask shift to analyze DPT effect on specific paths if needed Recommended 4 DPT corners for most P&R designs and flows 4 DPT corners expand the BEOL space to account for mask misalignment CmaxDPmax / RCmaxDPmax / CminDPmin / RCminDPmin CmaxDPmax CminDPmin RCmaxDPmax RCminDPmin Cmax As a conclusion, we recommend designers to apply the same five corners methodology but with replacing 4 green corners with 4 red ones (DPT-aware corners)  No increase in number of corners used That will increase slightly the design corners coverage to include DPT effects and shield designers from this added complexity We also provide Mask Shift capability just in case any designer needs to study DPT effects on a certain specific path and willing to go through the extra time and efforts We recommend DPT colorless flow due to its simplicity (does not need a colored GDS/database) and the close results it produces relative to DPT colored flow and Mask Shift flow No change needed in STA CAD flow and it showed small impact of DPT effects on setup timing as a function of routing density and number of DPT levels. However, DPT has minimal effect on Hold timing C RCmin Nominal RCmax Cmin R November 8, 2018

Extraction and STA Flow Recommendations Extraction Flow: Use colorless flow with DPT corners – no change needed to existing CAD flow STA Flow: No change needed to existing CAD flow – small impact on setup time due to DPT PEX corners, almost no impact on hold time Recommend Option 1a for most designs November 8, 2018

Q & A November 8, 2018

DPT Extraction of Simple Structures Using an interdigitized simple dense interconnect structure: Varying #of lines @min pitch from 2-20 lines Mask shift flow is our golden reference of accuracy Gives exactly same results as Manual layout shift Shifts “E2” mask in the GDS layout to the right/left relative to “E1” mask DPT corner flow: uses DPmax and DPmin extraction corners Compare DPT corner flow to the mask shift flow to analyze extraction accuracy ……… These two simple structures represent most of the situations in real designs (dense symmetrical designs and asymmetrical sparse designs). Manual shift is our base for comparison and it is done by shifting one mask relative to the other in the layout to capture what we expect to have on silicon from DPT misalignment Mask shift flow is letting the DPT-aware extraction tool to do the mask shift based on value and direction that we enter. We found that the mask shift flow gives EXACTLY the same results as manual shift, so we will use it as the golden reference for us through this work And then we compare the DPT corner flow to the mask shift flow under different scenarios November 8, 2018

DPmax and DPmin are good bounds DPT Extraction of Simple Structures: Results Observations: For #of interconnects >4, DPmax and DPmin provide good bounds DPmin corner bound not as tight on symmetric dense structures due to corner cases Case of 2 lines: Usually does not exist in real designs due to metal fill Case of 4 lines: Still one edge is direction sensitive but well bounded by DPmax & DPmin In case of Symmetrical structure, for any odd number of interconnects or even number > 4, the mask shift effect can be bounded between the No_Shift and Dpmax corner. Here the Dpmin corner is over estimating the reduction of coupling capacitance since almost all shifts are worse that No_shift situation But we need the Dpmin corner for the asymmetrical case as we will see in the next slide Y-axis is NOT %cap DPmax and DPmin are good bounds November 8, 2018