NA Silicon Wafer Committee Liaison Report Updated May 16, 2013

Meeting Information Last meeting Next meeting Tuesday, April 2, 2013, NA Spring Standards Meeting Intel, Santa Clara, CA Next meeting Tuesday, July 9, 2013, SEMICON West Francisco Marriott Marquis, CA www.semi.org/standards for the latest update

NA Silicon Wafer Committee Committee Chairmen Noel Poduje /SMS Dinesh Gupta /STA

Silicon Wafer Committee C: Dinesh Gupta - STA C: Noel Poduje – SMS VC: Mike Goldstein – Intel TE: Murray Bullis – Materials & Metrology Specifications Int’l Annealed Wafers TF Dinesh Gupta -STA Int’l 450 mm Wafers TF Mike Goldstein - Intel Int’l Epitaxial Wafers TF Dinesh Gupta - STA Int’l Polished Wafers TF Murray Bullis - Materials & Metrology Int’l SOI Wafers TF Mariam Sadaka- SOITEC Metrology Int’l Advanced Wafer Geometry TF Noel Poduje – SMS Jaydeep Sinha – KLA-Tencor John Valley - MEMC Int’l Advanced Surface Inspection TF George Kren - KLA-Tencor Committee Int’l Test Methods TF Int’l Terminology TF

Ballot results Doc. 5450A, Revision to SEMI M49-0912, with Title Change to: Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 16 nm Technology Generations Approved pending ISC A&R Review Doc. 5559, New Auxiliary Information: Interlaboratory Evaluation Of Nondestructive Method For Measuring The Edge Contour Of Silicon Wafers

New SNARFs Int’l Polished Wafer TF Int’l Annealed Wafer TF 11/8/2018 New SNARFs Int’l Polished Wafer TF Doc. 5543, Line Items Revision to SEMI M1-0413, Specifications for Polished Single Crystal Silicon Wafers SNARF was revised to allow additional line item changes Int’l Annealed Wafer TF Doc. 5583, Revision of SEMI M57-0413, Specifications for Silicon Annealed Wafers

Workshop at SEMICON West [1] Silicon Wafers – Future Standardization to Enable the Transition Since 2008, SEMI has published fifteen 450 mm wafer standards, guided by customer requirements and supplier feedback. These specifications, covering wafers, carriers, and loadports, have enabled the industry to continue the development of equipment, materials, interfaces, and processes, but further standardization will be necessary for a successful transition to manufacturing on 450mm wafers. Speakers from Intel, Samsung, and TSMC and others will introduce some of these new concepts during this seminar. Proposals discussed during this workshop will be considered for standization by the SEMI Standards Advanced Wafer Geometry Task Force under the Silicon Wafer Committee. Wednesday, July 10, 2013 (2:30-5:30 PM) San Francisco Marriott Marquis

Workshop at SEMICON West [2] Proposed Agenda 14:30 – 14:50: Mike Goldstein (Intel): Towards 450 mm Silicon Wafers 14:50 – 15:20: Kwangkook Lee (Samsung/G450C): New Edge Exclusion Proposal 15:20 – 15:50: Pinyen Lin (TSMC/G450C): Notchless Wafer 15:50 – 16:20: Gerd Pfeiffer (IBM): Wafer Geometry for Advanced Nodes 16:20 – 16:50: Hisashi Furuya (SUMCO): Challenges during 450 mm Silicon Processing 16:50 – 17:20: Allen Ware (F450C): 450 mm Facilities Planning 17:20 – 17:30: Q&A Registration at: SEMICONWEST.ORG or direct link at http://www.semiconwest.org/en/node/10536

11/8/2018 Ballots for Cycle 4-2013 Doc. 5543, Line Items Revision to SEMI M1-0413, Specifications for Polished Single Crystal Silicon Wafers Doc. 5541, Revision to SEMI M41-0707 Specification of Silicon-on-insulator (SOI) For Power Device/ICs

Metrology Group Int’l Advanced Wafer Geometry TF/Noel Poduje (SMS) & Jaydeep Sinha (KLA-Tencor) [1] Activities are well coordinated internationally EU - Doc. 5430A: Revision to M73, Test Methods for Extracting Relevant Characteristics from Measured Wafer Edge Profiles Ballot issued in cycle 1-2013 for review at West Drafting doc. 5343 Rev. to M49-1011, Guide For Specifying Geometry Measurement Systems For Silicon: NT and ZDD scaling from reference wafer

Metrology Group Int’l Advanced Wafer Geometry TF/Noel Poduje (SMS) & Jaydeep Sinha (KLA-Tencor) [2] Drafting doc. 5540, New Auxiliary Information, Illustration of Flatness and Shape Metrics for Silicon Wafers Drafting doc. 5539, Revision of SEMI MF1390-0707 (Reapproved 0512) ,Test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning

Metrology Group Int’l Advanced Surface Inspection TF/George Kren (KLA-Tencor), John Valley (MEMC) Drafting doc. 5503, Line Item Revision to M52-0912 Guide for Specifying Scanning Surface Inspection Systems for Silicon Wafers for the 130 nm to 11 nm Technology Generations (add M80 in reference) To address Shimizu-san’s negative Discussed SEMI M53 Model Based Calibration (MBC) - Proof of Concept

Specifications Group TF will continue to support the 450 mm program. 11/8/2018 Specifications Group Int’l 450 mm Wafer TF/Mike Goldstein (Intel) TF will continue to support the 450 mm program. Doc. 5442, Reapproval of SEMI M74-1108, Specification for 450 mm Diameter Mechanical Handling Polished Wafers Ballot passed at SEMICON Japan and published An Interest on 450 mm Notchless Wafer Standard was discussed by G450C See attached for presentations

Specifications Group Int’l Polished Wafer TF/Murray Bullis (Materials & Metrology) Doc. 5543, Line Items Revision of SEMI M1-0413, Specifications for Polished Single Crystal Silicon Wafers Ballot is issued for cycle 4-2013 for review at SEMICON West

Specifications Group Int’l SOI Wafer TF/Mariam Sadaka (SOITEC) Doc. 5541, Revision of SEMI M41-0707 Specification of Silicon-on-Insulator (SOI) for Power Device/Ics Ballot was issued for cycle 4-2013 for review at SEMICON West

Specifications Group Int’l Epitaxial Wafer TF/Dinesh Gupta (STA) Drafting doc. 5542, Line Item Revision to SEMI M62-0413, Specifications for Silicon Epitaxial Wafers Line items include: 1. Make Revision of Tables R2-7 & R2-8 - Change ¶3-2.7 Nanotopography value and related Footnote #9. 2. Add diameter information to Item 2-6.1 Table R2-7, R2-8 3. Add Some editorial changes

Specifications Group Int’l Annealed Wafer TF/Dinesh Gupta (STA) Drafting doc. 5583, Revision of SEMI M57-0413, Guide for Specifying Silicon Annealed Wafers Revision includes: Delete footnote 4 reference to 200mm diameter for 32nm and 2nm technology nodes Make the corrections to footnotes

Committee TF Int’l Terminology TF/Murray Bullis (Materials & Metrology) Revision SEMI M59-0211, Terminology for Silicon Technology No revision at the present time Future terms include: polysilicon, wafer packaging, microscopy and optics terms

Committee TF Int’l Test Methods TF/Dinesh Gupta (STA) Doc. 5313B Line Items Revision of SEMI MF1535-0707, Test Method for Carrier Recombination Lifetime in Silicon Wafers by Noncontact Measurement of Photoconductivity Decay by Microwave Reflectance Consensus is lacking. Revisions are ongoing. The discussion will be discussed at SEMICON

Contact For more information, please contact Kevin Nguyen at knguyen@semi.org