vs vb cc VDD M9 M12 M11 Iref M1 M2 vo vin- vin+= voQ = vo CL M3 M4 M13

Slides:



Advertisements
Similar presentations
Operational Amplifier Stability
Advertisements

The Operational Amplifiers Dr. Farahmand. Opamps Properties IdealPractical ArchitectureCircuits Open Loop Parameters Modes of operation Frequency Response.
Biomedical Instrumentation I
Instructor:Po-Yu Kuo 教師:郭柏佑
Solving Op Amp Stability Issues Part 4
ECE 342 – Jose Schutt-Aine 1 ECE 342 Solid-State Devices & Circuits 16. Active Loads Jose E. Schutt-Aine Electrical & Computer Engineering University of.
1 OPA277 Amplifier Stability Issue capacitive loads Iven Xu 12/14/2013.
OpAmp (OTA) Design The design process involves two distinct activities: Architecture Design –Find an architecture already available and adapt it to present.
Solving Op Amp Stability Issues Part 3 (For Voltage Feedback Op Amps) Tim Green & Collin Wells Precision Analog Linear Applications 1.
1 Amplifiers. Equivalent Circuit of a Voltage Amplifier G vo V i IoIo RoRo VoVo ViVi RiRi IiIi Amplifier ViVi VoVo (a) Black Box Representation.
CMOS AMPLIFIERS Simple Inverting Amplifier Differential Amplifiers Cascode Amplifier Output Amplifiers Summary.
CMOS AMPLIFIERS Simple Inverting Amplifier Differential Amplifiers Cascode Amplifier Output Amplifiers Summary.
2. CMOS Op-amp설계 (1).
Prepared by PATEL DEEP J. ENROLL. NO PATEL JAINIL K. ENROLL.NO PATEL ASHISH. ENROLL.NO PATEL APURV ENROLL.NO
TECHNIQUES OF DC CIRCUIT ANALYSIS: SKEE 1023
Recall Last Lecture Biasing of BJT Applications of BJT
Recall Last Lecture Biasing of BJT Three types of biasing
ECE 1270: Introduction to Electric Circuits
ANALOGUE ELECTRONICS CIRCUITS I
FET Amplifier Circuits Analysis
ECE 3302 Fundamentals of Electrical Engineering
ANALOGUE ELECTRONICS I
Recall Lecture 17 MOSFET DC Analysis
Electronic Devices Ninth Edition Floyd Chapter 12.
COMMON-GATE AMPLIFIER
Recall Last Lecture Introduction to BJT Amplifier
Recall Lecture 14 Introduction to BJT Amplifier
Oscillator Introduction of Oscillator Linear Oscillator Stability
ANALOGUE ELECTRONICS I
Design: architecture selection plus biasing/sizing
TECHNIQUES OF DC CIRCUIT ANALYSIS: SKEE 1023

VDD M3 M1 Vbb Vin CL Rb Vo VDD Vo Vb3
Fully differential op amps
Last time Small signal DC analysis Goal: Mainly use CS as example
CMOS Analog Design Using All-Region MOSFET Modeling
vs vb cc VDD VDD VDD M9 M12 M11 vo Iref M1 M2 vin vin+= voQ CL vf=vin

A general method for TF It’s systematic Uses Mason’s formula
OpAmp (OTA) Design The design process involves two distinct activities: Architecture Design Find an architecture already available and adapt it to present.
Basic BJT Small-Signal Model
M2 M1 Vbb Vin CL M4 M3 Vyy Vxx VDD VDD Vo<Vxx+|Vt3| flip up-down
OpAmp Design and compensation
VDD VDD VDD M2 M2 Iref vo+ vo- CL CL M1 M1 VoQ Voc vin- vin+ – + 2*M1.
VDD VDD Vo<VG6+|Vt6| =VDD - |Vtp| - 2Veff M7 M5 M8 M6 vo
For a differential amplifer: vin+=vic+vid/2, vin-=vic-vid/2
vs vin- vin+ vbp vbn vbn vbb vbb VDD VDD M9 M12 M1 M2 v- v+ Iref M3 M4
Last time Reviewed 4 devices in CMOS Transistors: main device
Miller equivalent circuit
Common mode feedback for fully differential amplifiers
Basic current mirror Small signal: Rin = 1/(gm1+gds1)  1/gm1
A MOSFET Opamp with an N-MOS Dfferential Pair
Operational Amplifier (Op-Amp)-μA741
Types of Amplifiers Common source, input pairs, are transconductance
VDD M2 M1 Vbb Vin CL RL Vo VDD Vo Vb2
Common mode feedback for fully differential amplifiers
Common source output stage:
Differential Amplifier
ELECTRONIC CIRCUIT ANALYSIS
vs vb cc VDD VDD VDD M9 M12 M11 vo Iref M1 M2 vin vin+= voQ CL vf=vin
Rail-to-rail Input Stage
Differential Amplifier
VDD Vin+ CL Vin- Vb3 folded cascode amp Vb2 Vb1 Vb4 Vb5.
A general method for TF It’s systematic Uses Mason’s formula
VDD VDD VDD M2 M2 Iref vo+ vo- CL CL M1 M1 VoQ Voc vin- vin+ – + 2*M1.
Common-Collector (Emitter-Follower) Amplifier
Common-Collector (Emitter-Follower) Amplifier
Recall Last Lecture Introduction to BJT Amplifier
Common-Collector (Emitter-Follower) Amplifier
Recall Last Lecture Introduction to BJT Amplifier
Presentation transcript:

vs vb cc VDD M9 M12 M11 Iref M1 M2 vo vin- vin+= voQ = vo CL M3 M4 M13

DC gain: Av(0)={gm1*(ro6,8||ro2,4)} * {gm10*(ro10||ro11) =Av1(0) * Av2(0) With Miller simplification: p1 = -1/{(Av2*Cc + Cgs10 +…)*(ro6,8||ro2,4)}  -1/{Av2*Cc*(ro6,8||ro2,4)} p2  - gm10/{CL+Cc+Cdb10+Cdb11} BW = |p1| GBW = Av(0)*BW  gm1/Cc

But Miller simplification gets rid of bridge cap, hence hides zero. Going back to schematics, examine vo1  io  vo io = vo1*(sCc – gm10) vo = io/(sCLtot + go) =vo1*(sCc – gm10)/(sCLtot + go)  z1  +gm10/Cc

wp1 gm10/CL A1(s)A2(s) A1(s) wp2 wz1 A2(s) w 0dB (s/z1 - 1) A(s)A(0)----------------------- (s/p1 - 1)(s/p2 - 1) UGF GBW

Phase Margin: PM = 180 +(A(s))= 180 +A(s) = 180 +(s/z1-1) - (s/p1-1) - (s/p2-1) = 180 – atan(GBW/z1) – 90 – atan(GBW/|p2|) = 90 – atan(gm1/gm10) – atan(GBW/|p2|)  Make GBW < 0.5 |p2| Make gm1 < 0.1 gm10

In the previous, we assumed  to be frequency-independent. How can we do that? Examine 3 cases: Buffer connection Resistive feedback Capacitive feedback

vs vb cc =1 VDD VDD VDD M9 M12 M11 Iref M1 M2 vo vin+= voQ Vin- = vo CL vb M3 M4 vo cc R _ + M5 M6 M10 M7 M8 vin2 =1

vs vb cc VDD VDD VDD M9 M12 M11 Iref M1 M2 vin- vo vin+= voQ CL M3 M4

vs vb cc VDD VDD VDD M9 M12 M11 vo Iref vin- M1 M2 vin+= voQ CL Rf M3 Ri cc R M5 M6 M10 M7 M8 vin2

  This is s-dependent. To create an s-independent b an, place a Cf in parallel with Rf, with Cf*Rf = Cin-*Ri. Then, is real.  

vs vb cc VDD VDD VDD M9 M12 M11 Iref M1 M2 vo vin- vin+= voQ CL M3 M4

vs vb cc VDD VDD VDD M9 M12 M11 vo Iref vin- M1 M2 vin+= voQ CL Cf M3 Ci cc R M5 M6 M10 M7 M8 vin2