Biological Processes…

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Presentation transcript:

Biological Processes… Computing Beyond CMOS Intense research into novel materials and devices: Carbon Nanotubes… Biological Processes… Molecular Switches… 5/31/07 IWLS 2007

! Computing Beyond CMOS c Many technologies still in exploratory phase: c ! 5/31/07 IWLS 2007

carbon nanowire crossbar Nanoscale Circuits Identify general traits that impinge upon logic synthesis: Features: High density of bits. Challenges: Topological constraints. Inherent randomness. High defect rates. carbon nanowire crossbar 5/31/07 IWLS 2007

Synthesis of Stochastic Logic Given a technology characterized by: High degree of structural parallelism. Inherent randomness in logic/interconnects. Synthesize: Circuit that computes a probability distribution corresponding to a logical specification. Strategy: Cast problem in terms of arithmetic operations. Perform synthesis with binary moment diagrams. 5/31/07 IWLS 2007

Probabilistic Bundles 1 x X 1 A real value x in [0, 1] is encoded as a stream of bits X. For each bit, the probability that it is one is: P(X=1) = x. 5/31/07 IWLS 2007

Arithmetic Operations Multiplication (Scaled) Addition b a B P A C c = ) ( ) 1 ( )] [ b s a B P S A C c - + = 5/31/07 IWLS 2007

Synthesis Strategy From circuit, construct a data structure called a multiplicative binary moment diagram (*BMD). Manipulate the *BMD into the right form. Implement a stochastic circuit with Shuffled AND gates and Bundleplexors. 5/31/07 IWLS 2007

Arithmetic Functions 4 3 2 1 x f - + = 5/31/07 IWLS 2007

Construct *BMD 4 3 2 1 x f - + = See R. Bryant, “Verification of Arithmetic Circuits with BMDs,” 1995. x f w R L + = 5/31/07 IWLS 2007

Split *BMD 4 3 2 1 x f - + = positive negative

Normalize 4 3 2 1 x f + = P X 4 3 2 1 x f - + = positive

Implement Stochastic Logic x w f R L X w SAND BUX x f R L X 5/31/07 IWLS 2007

Implement Stochastic Logic 5/31/07 IWLS 2007

Size of Stochastic Circuits #Device #Input #Output #StDevice Ratio C17 14 5 2 26 1.86 b1 18 3 4 1.00 majority 1 23 1.28 lion 19 30 1.58 cm138a 43 6 8 104 2.42 bbtas 44 74 1.68 cm42a 49 10 61 1.24 tcon 58 17 16 73 1.26 beecount 62 7 108 1.74 decod 69 194 2.81 sqrt8ml 87 1.18 sqrt8 79 1.10 c8 184 28 272 1.48 Average 1.54

Ratio of Bundle Widths to Scaling S Error Percentages Circuit S Ratio of Bundle Widths to Scaling S 5 10 20 50 100 C17 4 8.36 3.13 1.02 0.00 b1 3 5.63 1.72 0.16 majority 9 4.69 1.88 0.94 0.31 mc 6 3.97 2.12 0.42 0.07 cm138a 8 0.55 0.51 0.22 0.02 bbtas 7 5.84 1.91 0.78 0.09 cm42a 0.91 0.56 0.03 tcon 2 1.50 0.23 0.01 Decod 16 4.81 1.90 0.72 0.11 0.05 Sqrt8ml 24 3.56 1.76 0.82 0.39 0.04 Sqrt8 6.60 1.52 0.86 0.12 c8 5.93 3.09 1.03 Average 9.13 4.36 1.83 0.60